A device of measuring a duty cycle includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The control circuit is coupled to the resistor-capacitor circuit, and configured to acquire an ON-time according to the first voltage, the second voltage and the third voltage. The ON-time is a time interval during which the reference signal is in the first state.

A apparatus, method, system and medium are provided. The apparatus includes: a buffer chain, including N first buffers connected end to end, N first AND gates with one input connected to a pulse signal and the other input connected to an output of a corresponding first buffer, and N flip-flops coupled with outputs of respective first AND gates; a path time delay adjustment circuit, with an input receiving a pulse signal, and an output connected to an input terminal of the first buffer; a control apparatus, controlling the time delay produced by the adjustment circuit to be reduced by at least one step from a preset time delay during each adjustment until an output of a P.sup.th flip-flop flips; a measuring device measuring the pulse signal's width according to an output of each flip-flop, the time delay of each first buffer and the time delay of the adjustment circuit.

Methods and apparatus are described for detecting anomalies in a clock signal. Example methods include sensing a clock signal that exhibits alternating phases during normal operation; responsive to sensing the start of a first phase, generating a pulse; and if the pulse terminates before sensing the end of the first phase, asserting a clock stopped detection signal. Example clock anomaly detection apparatus includes a clock signal input for coupling to a clock signal that, during normal operation, oscillates between first and second clock states. An anomaly detection output is asserted if the clock signal remains in the first clock state longer than a first phase expected duration or remains in the second clock state longer than a second phase expected duration.

According to a method for filtering measurement data of a sensor system (2), light pulses (5) reflected in the environment of the sensor system (2) are captured by means of an array (7) of optical detectors (8, 9, 10). A multiplicity of measurement signals (11, 12) are generated by means of the array (7) based on the captured light pulses. A computing unit (3) identifies a first measurement signal (11) whose pulse energy is greater than a specified minimum energy, wherein the first measurement signal (11) was generated by a first detector (8). A second measurement signal (12) is compared with the first measurement signal (11) by means of the computing unit (3), wherein the second measurement signal (12) was generated by a second detector (9), which is at a distance from the first detector (8) that is less than or equal to a specified maximum distance. The computing unit discards at least a part of the second measurement signal depending on a result of the comparison.

A method and apparatus are described for compensating input voltage ripples of an interleaved boost converter using cycle times. In an embodiment, a phase compensator receives a first duty cycle measurement of a first converter and a second duty cycle measurement of a second converter, compares the first duty cycle to the second duty cycle and generates a phase compensation in response thereto. A phase combiner combines a phase adjustment output and the phase compensation and produces a phase control output, and a cycle controller is coupled to the first and the second converters to generate a first drive signal to control switching of the first converter and to generate a second drive signal to control switching of the second converter, wherein a time of the second drive signal is adjusted using the phase control output.

A device of measuring a duty cycle includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The control circuit is coupled to the resistor-capacitor circuit, and configured to acquire an ON-time according to the first voltage, the second voltage and the third voltage. The ON-time is a time interval during which the reference signal is in the first state.

Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.

A tire monitoring apparatus comprising a monitor installed on a tire and a pulse width measuring apparatus for measuring the width of pulses produced by the monitor. The pulse width measuring apparatus comprises a frequency analyzer for producing a frequency representation of the pulse, a signal processor for determining a minimum value of the frequency representation, and a pulse width estimator that inverts the minimum value to produce a measurement for the pulse width. The tire monitoring apparatus uses the pulse width measurement as an indication of characteristics of the tire.

The present invention comprises a novel system and method to detect and estimate the time-frequency span of wireless signals present in a wideband RF spectrum. In preferred embodiments, the Faster RCNN deep learning architecture is used to detect the presence of wireless transmitters from the spectrogram images plotted by searching for rectangular shapes of any size, then localize the time and frequency information from the output of the FRCNN deep learning architecture.

Disclosed are circuit and method for width measurement of digital pulse signals. The circuit comprises: a sample clock, used to drive all registers in the circuit; an edge detection and interrupt control unit, used to detect a rising edge and a falling edge of a pulse signal on an input pin Input to control signal collection; an integer encoding unit comprising a counter and registers and used to measure an integer part μ of the width of a high or low level on the input pin Input with one period 1/f of the sample clock as a reference unit; a signal capture chain, used to sample an output level of each delay cell DLL; a decimal encoding unit, used to find out and record the propagation position of the pulse edge on the signal capture chain; and a calibration control unit, used to perform calibration.