A device of measuring a duty cycle includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The control circuit is coupled to the resistor-capacitor circuit, and configured to acquire an ON-time according to the first voltage, the second voltage and the third voltage. The ON-time is a time interval during which the reference signal is in the first state.

Methods and apparatus are described for detecting anomalies in a clock signal. Example methods include sensing a clock signal that exhibits alternating phases during normal operation; responsive to sensing the start of a first phase, generating a pulse; and if the pulse terminates before sensing the end of the first phase, asserting a clock stopped detection signal. Example clock anomaly detection apparatus includes a clock signal input for coupling to a clock signal that, during normal operation, oscillates between first and second clock states. An anomaly detection output is asserted if the clock signal remains in the first clock state longer than a first phase expected duration or remains in the second clock state longer than a second phase expected duration.

A duty timing detector includes: a control logic, the control logic being configured to: receive an input toggle signal and an output toggle signal that corresponds to the input toggle signal, and generate a difference signal using a difference between a duty of the input toggle signal and a duty of the output toggle signal; a first low-pass filter configured to output a DC input voltage based on a pulse width of the input toggle signal; a second low-pass filter configured to output a DC difference voltage based on a pulse width of the difference signal; a compensation circuit configured to compensate the duty of the output toggle signal using the DC input voltage and the DC difference voltage; and an oscillator configured to generate a duty-compensated output toggle signal, and to provide the duty-compensated output toggle signal to the control logic.

The present invention provides a method for analyzing flow regime alterations from reservoir inflow to reservoir outflow, including: acquiring a reservoir inflow data series and a reservoir outflow data series, and determining a local water year of reservoir inflow and reservoir outflow; calculating low and high pulses thresholds of indicators of hydrologic alteration (IHA) for reservoir inflow, and environmental flow thresholds of environmental flow component (EFC) for the reservoir inflow; applying thresholds required for low pulse and high pulse of IHA and the environmental flow thresholds of EFC to reservoir outflow, and respectively calculating IHA parameters and EFC parameters of the inflow and the outflow; and using the range of variability approach (RVA) based on IHA and EFC to analyze the flow regime alterations from the reservoir inflow to the reservoir outflow according to the IHA parameters and the EFC parameters of the reservoir inflow and the reservoir outflow.

A duty timing detector includes: a control logic, the control logic being configured to: receive an input toggle signal and an output toggle signal that corresponds to the input toggle signal, and generate a difference signal using a difference between a duty of the input toggle signal and a duty of the output toggle signal; a first low-pass filter configured to output a DC input voltage based on a pulse width of the input toggle signal; a second low-pass filter configured to output a DC difference voltage based on a pulse width of the difference signal; a compensation circuit configured to compensate the duty of the output toggle signal using the DC input voltage and the DC difference voltage; and an oscillator configured to generate a duty-compensated output toggle signal, and to provide the duty-compensated output toggle signal to the control logic.

A device of measuring a duty cycle includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The control circuit is coupled to the resistor-capacitor circuit, and configured to acquire an ON-time according to the first voltage, the second voltage and the third voltage. The ON-time is a time interval during which the reference signal is in the first state.

Embodiments herein relate to an apparatus comprising: a first circuit with a plurality of stages; and a second circuit communicatively coupled with the first circuit, wherein the second circuit includes: a plurality of tap lines, wherein respective tap lines of the plurality of tap lines are coupled between two stages of the plurality of stages; and the logic, wherein the logic is to identify, based on an average voltage measurement of at least one tap line, a status of a duty-cycle of a signal propagating through a stage of the first circuit. Other embodiments may be described and claimed.

In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.

The invention relates to a detection apparatus (12) for detecting photons. The detection apparatus comprises a pile-up determining unit (15) for determining whether detection signal pulses being indicative of detected photons are caused by a pile-up event or by a non-pile-up event, wherein a detection values generating unit (16) generates detection values depending on the detection signal pulses and depending on the determination whether the respective detection signal pulse is caused by a pile-up event or by a non-pile-up event. In particular, the detection values generating unit can be adapted to reject the detection signal pulses caused by pile-up events while generating the detection values. This allows for an improved quality of the generated detection values.

A device for the detection of an ultra wide band signal, including a signal reception circuit, a signal divider circuit to divide the received signal into several frequency sub-bands, a circuit to determine the amplitude and duration of the received signal in each frequency sub-band, a circuit to compare the amplitude of the signal received in each frequency sub-band with an amplitude threshold, a circuit to compare the duration of the signal received in each frequency sub-band with a time threshold, and a decision circuit that determines that the received signal is of the ultra wide band type if the amplitude of the signal received in each frequency sub-band is higher than the amplitude threshold and if the duration of the signal received in each frequency sub-band is less than the time threshold.