Enhanced probe cards, for testing unpackaged semiconductor die including numerous discrete devices (e.g., LEDs), are described. The die includes anodes and cathodes for the LEDs. Via a single touchdown event, the probe card may simultaneously operate each of the LEDs. The LEDs' optical output is measured and the performance of the die is characterized. The probe card includes a conductive first contact and another contact that are fabricated from a conformal sheet or film. Upon the touchdown event, the first contact makes contact with each of the die's anodes and the other contact makes contact with each of the die's cathodes. The vertical and sheet resistance of the contacts are sufficient such that the voltage drop across the vertical dimension of the contacts is approximately an order of magnitude greater than the operating voltage of the LEDs and current-sharing between adjacent LEDs is limited by the sheet resistance.

An inspection apparatus includes a light sensor that detects light from a semiconductor device to which an electric signal has been input, an optical system that guides light from the semiconductor device to the light sensor, and a control device electrically connected to the light sensor. The control device includes a measurement unit that acquires waveform data obtained by optical measurement for each of a plurality of positions on a defective semiconductor device and waveform data obtained by the optical measurement for each of a plurality of positions on a non-defective semiconductor device, a calculation unit that calculates a degree of correspondence between the waveform data of the defective semiconductor device and the waveform data of the non-defective semiconductor device, and an analysis unit that analyzes a defective part of the defective semiconductor device on the basis of the degree of correspondence for each of the plurality of positions.

The invention is a cost effective multisite parallel wafer tester that has an array of stationary wafer test sites; a single mobile wafer handling and alignment carriage that holds a wafer handling robot, a wafer rotation pre-alignment assembly, a wafer alignment assembly, a wafer front opening unified pod (FOUP), and a wafer camera assembly; and a robot that moves the wafer handling and alignment carriage to and from each test site. Each test site contains a wafer probe card assembly and a floating chuck. In use, wafers are loaded from a front opening FOUP into a wafer buffer FOUP from which wafers are retrieved by the wafer handling and alignment assembly. The robot positions the wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly in front of and inside a given test site and aligns the wafer to be tested with the probe card inside the test site using the floating chuck.

A method of testing an integrated circuit of a device is described. Air is allowed through a fluid line to modify a size of a volume defined between the first and second components of an actuator to move a contactor support structure relative to the apparatus and urge terminals on the contactor support structure against contacts on the device. Air is automatically released from the fluid line through a pressure relief valve when a pressure of the air in the fluid line reaches a predetermined value. The holder is moved relative to the apparatus frame to disengage the terminals from the contacts while maintaining the first and second components of the actuator in a substantially stationary relationship with one another. A connecting arrangement is provided including first and second connecting pieces with complementary interengaging formations that restricts movement of the contactor substrate relative to the distribution board substrate in a tangential direction.

The present disclosure provides a semiconductor testing apparatus with a connected unit, which is applied to a wafer probing testing or a final testing. The semiconductor testing apparatus comprises a semiconductor testing printed circuit board, a functional module and the connected unit. First contact points are disposed on a first surface of the semiconductor testing printed circuit board, and electrically connected to the functional module. Second contact points are disposed on a second surface of the semiconductor testing printed circuit board, and electrically connected to a functional controller. The first contact points and the second contact points have independent and non-interfering working time domains. Therefore, the present disclosure can utilize the area of the semiconductor testing printed circuit board, and can independently perform functional testing of a wafer or packaged integrated circuit devices using multiple time domains, in a multi-time domain, synchronous or asynchronous manner.

A method and device for adapting temperatures of semiconductor components. The device includes a first and second semiconductor component, and an evaluation unit. The evaluation unit is configured to ascertain a first and second temperature of the first and second semiconductor component, respectively, calculate a first and second temperature deviation, which represents a deviation of the first and second temperature from a reference temperature, respectively, and adapt a first gate voltage of the first semiconductor component and/or a second gate voltage of the second semiconductor component until the first temperature deviation and the second temperature deviation are smaller than or equal to a predefined maximum allowable temperature deviation from the reference temperature. The adaptation takes place only when a predefined allowable control range for the respective gate voltage is not exceeded, and when the first temperature and/or the second temperature is/are greater than the reference temperature.

A board-like connector, a dual-arm bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-arm bridges spaced apart from each other and an insulating layer. Each of the dual-arm bridges includes a carrier, a first cantilever, a second cantilever, a first abutting column, and a second abutting column, the latter two of which extend from the first and second cantilevers along two opposite directions. The first cantilever and the second cantilever extend from and are coplanar with the carrier. The insulating layer connects the carriers of the dual-arm bridges. The first abutting column and second abutting column of each of the dual-arm bridges respectively protrude from two opposite sides of the insulating layer, and are configured to abut against two boards, respectively.

The present disclosure provides an electrical test structure, a semiconductor structure and an electrical test method. In the electrical test structure, in a first direction, the electrical test structure includes a first layer, an interconnect hole and a second layer arranged in a stack, and the interconnect hole is in contact with the first layer; the second layer includes a body part and a test part, and the test part is connected to the body part; the interconnect hole is configured as, when an offset distance of the interconnect hole relative to a preset position in a second direction is less than a first preset distance, or an offset distance of the interconnect hole relative to the preset position in a third direction is less than a second preset distance, the interconnect hole is spaced apart from the test part.

A contact probe for electronic tests includes an upper part having an end portion for contacting a first electronic component; a lower part having an end for contacting a second electronic component; and an elongated and deformable central body interposed between the upper and lower parts. The lower part has an enlarged head with a lower surface intended to rest at least partially onto a horizontal surface, the lower surface having an inclination angle from the horizontal surface onto which it rests when the probe is unbuckled and, when the probe is buckled, it can assume a position in which the lower surface moves to rest entirely onto the horizontal surface, thereby eliminating the inclination angle.

The present disclosure provides a method and a device for testing a wafer, an electronic device, and storage medium, wherein the method includes: obtaining plural test sheets; dividing the wafers to be tested in the plurality of test sheets according to individual test items in the plurality of test sheets, and determining the wafers to be tested corresponding to individual divided units; determining a test sequence of the test items to be performed on each wafer to be tested, based on a test sequence condition of the test items in individual test sheets and a test condition of a testing machine corresponding to individual divided units; and testing the wafer to be tested, according to the test sequence of the test items to be performed on any of the wafers to be tested.