A substrate support includes a supporting unit and a light irradiation mechanism. The supporting unit includes a plate member on which an inspection target is placed and a transparent member. The light irradiation mechanism is configured to irradiate light to increase a temperature of the inspection target. Each of the plate member and the transparent member is made of a low thermal expansion material having a linear expansion coefficient of 1.0×10.sup.−6/K or less.

A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.

The present disclosure relates to a method for estimating parameters of a junction of a power semi-conductor element comprising: •—Detecting at least one stable on-line operating condition through measurements (2, 3, 4) of Von, Ion, Tc on a semi-conductor module (1) where Ion is a current for which the on-state voltage Von of the semi-conductor is sensitive to the temperature and Tc is the temperature of the casing of said semi-conductor element; •—Measuring and storing at least one parameter set Von, Ion, Tc of said at least one stable operating condition; •—in a calculating unit (52), providing calculations for minimizing the error between a junction temperature estimation Tj of an electrical model Tj=F(Von, Ion, θelec) comprising a first set of unknown parameters θelec and another junction temperature estimation Tjmod of a loss/thermal model Tj=G(lon, Tc, θ mod) comprising a second set of unknown parameters θ mod and obtaining at least one set of parameters θelec and at least one parameter θ mod providing minimization of said error; •—providing the calculated value of Tj with at least one of the calculated parameters sets θelec and/or θ mod and the measured Von, Ion, Tc; •—Storing the at least one parameters set θelec and/or θ mod and/or Tj.

A method for detecting abnormity of a machine slot includes the following operations. A first failure rate is obtained. A second failure rate is obtained. A slot, of which the second failure rate is greater than or equal to the abnormity value, is marked as a target slot, and A slot, of which the second failure rate is smaller than the abnormity value, is marked as a control slot. An significance level of a difference between a failure rate of the target slot and a failure rate of the control slot in each day of the second time period is checked.

A method for in situ threshold voltage determination of a semiconductor device includes sourcing a current to a first terminal of the semiconductor device. A gate terminal of the semiconductor device is driven with a plurality of gate levels. Each gate level includes one of a plurality of different gate voltages. A transistor voltage is measured between the first terminal and a second terminal of the semiconductor device during each gate level. The respective gate voltage is stored in response to the semiconductor device voltage transitioning past a voltage limit. A temperature dependent threshold voltage of the semiconductor device is estimated for a first measured temperature measured during the storing of the stored gate voltage from a previously stored gate voltage and a second measure temperature.

A system to monitor a MOSFET, the system including a switching arrangement configured to switchably isolate a gate terminal of the MOSFET and a source terminal of the MOSFET from a gate-control voltage source and a test circuit configured to detect a change in a gate-to-source voltage of the MOSFET over a test period, the test period occurring while the gate terminal and the source terminal are isolated

A method for controlling temperature in a temperature control system. The method includes providing a temperature control system including a controller, a first contactor assembly having a first channel system, a plurality of first contacts, each of the first contacts including a portion that is disposed within the first channel system, and one or more of a first exhaust valve or a first inlet valve, and a second contactor assembly having a second channel system, a plurality of second contacts, each of the second contacts including a portion that is disposed within the second channel system, and one or more of a second exhaust valve or a second inlet valve. The method also includes receiving, by the first contactor assembly, a fluid at a first temperature. The method also includes receiving, by the second contactor assembly, the fluid at the first temperature.

A power conversion device including a switching element includes: a temperature change estimation unit estimating temperature change in a semiconductor chip containing the switching element; a number calculator calculating the number of power cycles to fracture of the semiconductor chip due to power cycles; and a degradation degree calculator computing a degree of degradation of the semiconductor chip caused by the power cycles. The temperature change estimation unit calculates a maximum value and a minimum value of temperature of the semiconductor chip in one power cycle based on a first threshold of temperature fall allowed when it is determined that the temperature of the semiconductor chip is rising, and a second threshold of temperature rise allowed when it is determined that the temperature of the semiconductor chip is falling. The number calculator calculates the number of power cycles to fracture based on the maximum value and the minimum value.

The present invention provides a system and method for measuring intermittent operating life (IOL) of a GaN-based device under test (DUT) is provided. The system is operable in a stressing mode, a cooling mode and a measure mode. A power regulation approach is adopted to ensure that DUT of the same thermal resistance have same temperature increase during the IOL test. The present invention eliminates the influence caused by parasitic parameters of testing circuits and the inconsistency of threshold voltage and drain-source resistance of the device itself. Through power regulation, it is the junction temperature of the device, not the housing temperature of the device, being directly controlled. Therefore, higher measurement accuracy can be achieved.

A safety container for high-power, electronic device testing, the safety container including a first shell and first and second ports in the first shell. The first shell is configured to substantially surround a testing chamber sized to accommodate a device-under-test (DUT). The first shell is substantially rigid. The first port is configured to allow a fluid into the testing chamber, the second port configured to allow the fluid to exit the testing chamber.