Embodiments of the present application disclose a fixing device and fixing method for chip test and a chip tester. The fixing device for chip test includes: a carrier with a fixing chamber for fixing a chip formed inside, a plurality of adjustors being disposed on sidewalls of the fixing chamber and configured to be extended or retracted to adjust a position of the chip in two orthogonal directions within a horizontal plane; and a top cover configured to cooperate with the carrier to fix the chip in a vertical direction, wherein at least one adjustable pressing cover is disposed at a bottom of the top cover, so as to autonomously adjust a pressing force applied to the chip by the pressing cover in the vertical direction. The present application is suitable for fixing chips with various overall dimensions, and can adaptively adjust a pressing force.

A detection circuit and an integrated circuit. The detection circuit is used for detecting the drift or an open circuit of a first capacitor (C1) on a filtered second power source terminal (220), and the second power source terminal (220) is suitable for acquiring a power source voltage from an unfiltered first power source terminal (210) by means of a first resistor (R1), and is suitable for being coupled to a reference electric potential terminal (230) by means of the first capacitor (C1). The detection circuit comprises a second resistor (R2) and a second capacitor (C2) that are connected in series and coupled between the first power source terminal (210) and the reference electric potential terminal (230), wherein the second resistor (R2) and the second capacitor (C2) have the same time constant as the first resistor (R1) and the first capacitor (C1).

A power monitor includes a detecting circuit, a processing circuit, and a warning circuit. The detecting circuit detects a first abnormal condition of a primary side circuit and a second abnormal condition of a secondary side circuit. The processing circuit calculates a first class and a first occurring number of the first abnormal condition, and calculates a second class and a second occurring number of the second abnormal condition. The processing circuit determines whether the first occurring number is larger than a first predetermined number corresponding to the first class; if it is, the processing circuit outputs a first abnormal signal. The processing circuit determines whether the second occurring number is larger than a second predetermined number corresponding to the second class; if it is, the processing circuit outputs a second abnormal signal. The warning circuit outputs a warning signal according to the first or the second abnormal signal.

An apparatus for testing a transducer module includes a test signal generator coupled to a common-mode terminal common to a plurality of transducers, and a signal processing circuit configured to receive output signal from each of said transducers and to produce an output signal. If the transducers are well matched to one another, the output signal will have little or no output amplitude. If there is a mismatch between the transducers, however, the output signal will have an amplitude proportional to the mismatch. The amplitude of the output signal may be compared to a predetermined threshold in order to produce a mismatch output signal indicating the existence of, and/or the degree of, mismatch between the transducers.

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

A method and system are directed to designing a low-dropout regulator (LDO) circuit and using the LDO circuit to detect recycled counterfeit integrated circuits. The LDO circuit includes, in part, a reference path circuit and a stressed path circuit. Each of the reference path circuit and the stressed path circuit is coupled to a control signal that can enable the corresponding path circuit for the LDO. LDO parameters can then be measured while the reference path circuit and the stressed path circuit is enabled respectively. The difference between the LDO parameters measured while the reference path circuit is enabled and while the stressed path circuit is enabled is used to determine if an integrated circuit comprising the LDO circuit is a recycled counterfeit.

The present invention provides a system and method for analysis of integrated circuit testing anomalies based on deep learning. Through repeated training by deep learning with historical test data accumulated during testing, automatic optimization of parameter settings depending on learning and training conditions is made possible. Moreover, based on real-time test data, testing anomalies can be predicted and early warnings against them can be provided to allow advanced intervention for preventing their occurrence. Additionally, for testing anomalies that have occurred, solutions can be automatically identified and provided, which shorten the times taken by different technicians to address the anomalies, resulting in more effective utilization of the equipment and lower testing cost.

The present disclosure provides a wafer probe card including: a non-magnetic printed circuit board (PCB) having a first side and a second side opposite the first side, the first side configured to face a magnet; a plurality of connection structures provided on the first side of the non-magnetic PCB; and a Hall sensor unit fixedly provided on the first side of the non-magnetic PCB, the Hall sensor electrically connected to at least one of the plurality of connection structures.

Systems and methods are provided for Integrated Circuit (IC) identification, authentication, and tamper detection. Die identification, authentication, and tamper detection techniques are described that employ capacitive sensing of on-chip interconnect. The signal and power routing in ICs have nominal capacitance values that are characteristic of their foundry, and the variance of these values, due to process tolerances, is unique to each device. Measuring these capacitances provides not only support for determining the authenticity of the device and fabrication site, but also provides distinct identification of each part. By integrating Capacitance-to-Digital Converters (CDCs) with low power and area overhead, capacitance values from intrinsic functional nets can be reported, and the need for separate additive test circuitry can be avoided.

A method and system for evaluating test data, a wafer test system, and a storage medium are provided. The method for evaluating test data includes: obtaining test data of a plurality of test programs, each test program including a plurality of test items; for each test program, calculating a correlation coefficient of each test item according to the test data; drawing a difference analysis graph for every two test programs in the plurality of test programs according to the correlation coefficient between each of the test items in different test programs, where a horizontal axis and a longitudinal axis of the difference analysis graph respectively correspond to one test program; and evaluating a difference of each test item in two different test programs according to the difference analysis graph.