The disclosure describes to techniques for detecting field failures or performance degradation of circuits, including integrated circuits (IC), by including additional contacts, i.e. terminals, along with the functional contacts that used for connecting the circuit to a system in which the circuit is a part. These additional contacts may be used to measure dynamic changing electrical characteristics over time e.g. voltage, current, temperature and impedance. These electrical characteristics may be representative of a certain failure mode and may be an indicator for circuit state-of-health (SOH), while the circuit is performing in the field.

The disclosure describes to techniques for detecting field failures or performance degradation of circuits, including integrated circuits (IC), by including additional contacts, i.e. terminals, along with the functional contacts that used for connecting the circuit to a system in which the circuit is a part. These additional contacts may be used to measure dynamic changing electrical characteristics over time e.g. voltage, current, temperature and impedance. These electrical characteristics may be representative of a certain failure mode and may be an indicator for circuit state-of-health (SOH), while the circuit is performing in the field.

Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

A method for testing a signal path in a sensor, the signal path including a filter circuit and a comparator circuit, the method including: closing a first signal line that is arranged to bypass a first capacitor in the filter circuit; injecting a test signal into the signal path after the first signal line is closed; and detecting whether a signal that is output by the comparator circuit in response to the test signal satisfies a predetermined condition.

The disclosure provides high voltage interlock circuit and detection method. The circuit comprises: a power module, a positive electrode of the power module being connected to one end of a current generating module; the current generating module, the other end of the current generating module being connected to a first terminal of a high voltage component module to inject a constant DC current into the high voltage component module; a first voltage dividing module, one end of the first voltage dividing module being connected to a second terminal of the high voltage component module, and the other end of the first voltage dividing module being connected to a negative electrode of the power module and a power ground; and a processing module to determine a fault of the high voltage component module based on a first voltage collected from the second terminal of the high voltage component module.

The disclosure provides high voltage interlock circuit and detection method. The circuit comprises: a power module, a positive electrode of the power module being connected to one end of a current generating module; the current generating module, the other end of the current generating module being connected to a first terminal of a high voltage component module to inject a constant DC current into the high voltage component module; a first voltage dividing module, one end of the first voltage dividing module being connected to a second terminal of the high voltage component module, and the other end of the first voltage dividing module being connected to a negative electrode of the power module and a power ground; and a processing module to determine a fault of the high voltage component module based on a first voltage collected from the second terminal of the high voltage component module.

A system may include a trim circuit configured to provide a trim signal to a circuit under test. The trim circuit may be configured to adjust a trim value of the trim signal based on a selection signal and a value signal. The trim signal may cause a key characteristic of the circuit under test to change based on the adjusted trim value. The system may include a production tester configured to determine whether the key characteristic is within a threshold range. Responsive to the key characteristic being within the threshold range, the production tester may stop performing the trim procedure on the circuit under test. Responsive to the key characteristic not being within the threshold range, the production tester may adjust the value signal based on whether the key characteristic is greater than or less than the threshold range.

A method for calibrating an electronic assembly during a manufacturing process is provided, including the steps: determining a calibration value for the assembly which for a predefined input value gives a deviation between an actual output value output by the assembly and a predefined desired output value, transmitting the calibration value to the assembly, and storing the calibration value in the assembly, wherein the calibration value of the assembly is determined by a machine learning method executed in a calibration device, and the machine learning method is trained by training data, which include historical calibration values of a plurality of assemblies of the same type and parameters of assemblies of the same type, which are dependent on the manufacturing process and/or express physical properties.

An integrated circuit (IC) includes: a first functional analog pin or pad; a first analog test bus coupled to the first functional analog pin or pad; first and second analog circuits coupled to the first analog test bus; and a test controller configured to: when the IC is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keep disconnected an input or output of the second analog circuit from the first analog test bus, and when the IC is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus.