Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

A method of measuring superconducting critical current in persistent mode using superconducting closed loops which allow the persistent current to flow without any joints. This persistent critical current is different than traditional resistive critical current that is the upper limit of the superconducting current carrying capacity, and provides the information about the range of critical current in persistent mode that is more close to applications in MRI, SMES, and Maglev operations. The measurement can be used as a quality control method in the manufacturing process and a piece of crucial information to magnet manufacturers for the design and fabrication of magnet. The superconducting materials include the second generation superconducting wires (coated conductors) based on Rare Earth (RE) Barium Copper Oxide superconducting material (REBa.sub.2Cu.sub.3O.sub.6+x, REBCO), or any other type of superconducting wires that can be manufactured in the form of tape.

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

An apparatus for controlling and monitoring the lifetime of a superconducting fault current limiter. The apparatus may include a processor; and a memory unit coupled to the processor, including a lifetime routine, where the lifetime routine is operative on the processor to monitor the superconducting fault current limiter. The lifetime routine may include a lifetime estimation processor to receive a set of fault information for a fault event of a superconductor tape of the superconducting fault current limiter, determine a present state of the superconductor tape based upon the set of fault information, and determine an estimated lifetime of the superconductor tape based upon the present state. The present state may be determined from additional information such as fault history on the superconducting fault current limiter, as well as a database of superconductor tape behavior with respect to various faults.

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

A measurement current (i) is injected into an active part (4) of an HTS superconductor. The active part is cooled, but not reservoirs (1, 2) from/to which the superconductor is wound. Only a fraction of the active part is exposed to a magnetic field for testing the electrical properties of the superconductor. Buffer devices (20a, 20b) prevent current sharing from outside the active part. The measurement current is injected where the residual magnetic field is at least 3 times lower than the magnetic field for testing, and/or the local critical current at the current injection locations is at least three times higher than the critical current at the magnetic field for testing. The electrical properties, e.g. the critical current, are tested by determining an integral of a voltage drop (U) across the active part, e.g. between two voltage pick-up elements (15a, 15b), as a function of measurement time ().

A method of measuring superconducting critical current in persistent mode using superconducting closed loops which allow the persistent current to flow without any joints. This persistent critical current is different than traditional resistive critical current that is the upper limit of the superconducting current carrying capacity, and provides the information about the range of critical current in persistent mode that is more close to applications in MRI, SMES, and Maglev operations. The measurement can be used as a quality control method in the manufacturing process and a piece of crucial information to magnet manufacturers for the design and fabrication of magnet. The superconducting materials include the second generation superconducting wires (coated conductors) based on Rare Earth (RE) Barium Copper Oxide superconducting material (REBa.sub.2Cu.sub.3O.sub.6+x, REBCO), or any other type of superconducting wires that can be manufactured in the form of tape.

An apparatus for controlling and monitoring the lifetime of a superconducting fault current limiter. The apparatus may include a processor; and a memory unit coupled to the processor, including a lifetime routine, where the lifetime routine is operative on the processor to monitor the superconducting fault current limiter. The lifetime routine may include a lifetime estimation processor to receive a set of fault information for a fault event of a superconductor tape of the superconducting fault current limiter, determine a present state of the superconductor tape based upon the set of fault information, and determine an estimated lifetime of the superconductor tape based upon the present state. The present state may be determined from additional information such as fault history on the superconducting fault current limiter, as well as a database of superconductor tape behavior with respect to various faults.