In some embodiments method comprises depositing a ferroelectric layer on a top surface of a semiconductor wafer and forming one or more gaps in the ferroelectric layer. The one or more gaps can be formed on a repetitive spacing to relieve stresses between the ferroelectric layer and the semiconductor wafer. A first dielectric layer is deposited over the ferroelectric layer and the first dielectric layer is planarized to fill in the gaps. A second dielectric layer is formed between the ferroelectric layer and the semiconductor wafer. The second dielectric layer can be formed by annealing the wafer in an oxidizing atmosphere such that an upper portion of the semiconductor substrate forms an oxide layer between the semiconductor substrate and the ferroelectric layer.

In particular the present invention relates to polymeric composition comprising scattering particles for lightning applications or light guides. The invention also relates to a process for manufacturing such a polymeric composition comprising scattering particles for lightning applications or light guides. More particularly the present invention relates to a polymeric (meth)acrylic composition comprising inorganic scattering particles for lightning applications or light guides.

Various embodiments provide for systems and techniques for the successful fabrication of metal oxide (TMO)-on-glass layer stacks via direct deposition. The resulting samples feature epitaxial, strontium titanate (STO) or barium titanate (BTO) films on silicon dioxide (SiO.sub.2) layers, forming STO- or BTO-buffered SiO.sub.2 pseudo-substrates. As the integration of TMO films on silicon rely on an STO or BTO buffer layer, a wide variety of TMO-based integrated devices (e.g., circuits, waveguides, etc.) can be fabricated from the TMO-on-glass platform of the present technology. Moreover, the STO, or the BTO, survives the fabrication process without a corresponding degradation of crystalline quality, as evidenced by various objective measures.

In some embodiments method comprises depositing a ferroelectric layer on a top surface of a semiconductor wafer and forming one or more gaps in the ferroelectric layer. The one or more gaps can be formed on a repetitive spacing to relieve stresses between the ferroelectric layer and the semiconductor wafer. A first dielectric layer is deposited over the ferroelectric layer and the first dielectric layer is planarized to fill in the gaps. A second dielectric layer is formed between the ferroelectric layer and the semiconductor wafer. The second dielectric layer can be formed by annealing the wafer in an oxidizing atmosphere such that an upper portion of the semiconductor substrate forms an oxide layer between the semiconductor substrate and the ferroelectric layer.

A hybrid photonic chip comprising a plurality of semiconductor materials arranged to define a chip providing a function, wherein at least a first part of the chip is formed of materials which can be fabricated using a CMOS technique; and at least a second part of the chip which comprises non-linear crystal material and is not subjected to etching process; wherein the second part of the chip in conjunction with the first part is configured to support a propagating low loss single mode.

Systems and methods describe growing RE-based integrated photonic and electronic layered structures on a single substrate. The layered structure comprises a substrate, an epi-twist rare earth oxide layer over a first region of the substrate, and a rare earth pnictide layer over a second region of the substrate, wherein the first region and the second region are non-overlapping.

A wafer includes a silicon layer, a first dielectric layer on the silicon layer, and a ferroelectric layer on the first dielectric layer. The ferroelectric layer defines one or more gaps between portions of the ferroelectric layer. The wafer also includes a second dielectric layer on the ferroelectric layer and disposed within the one or more gaps.

A hybrid photonic chip comprising a plurality of semiconductor materials arranged to define a chip providing a function, wherein at least a first part of the chip is formed of materials which can be fabricated using a CMOS technique; and at least a second part of the chip which comprises non-linear crystal material and is not subjected to etching process; wherein the second part of the chip in conjunction with the first part is configured to support a propagating low loss single mode.

Systems and methods describe growing RE-based integrated photonic and electronic layered structures on a single substrate. The layered structure comprises a substrate, an epi-twist rare earth oxide layer over a first region of the substrate, and a rare earth pnictide layer over a second region of the substrate, wherein the first region and the second region are non-overlapping.

An optical device comprises a photonic integrated circuit having an optical mode coupler. The optical mode coupler optically couples a first planar optical waveguide having a first optical core at one horizontal plane to a second planar optical waveguide having a second optical core at a different second horizontal plane. The optical mode coupler comprises two or more intermediate optical layers stacked vertically between the horizontal planes of the optical cores, and intermediate optical layer comprises one or more optical rails. The optical mode coupler causes light received from the first planar optical waveguide to excite an optical mode and guide the light of the optical mode such that the optical mode substantially overlaps the first planar optical waveguide and the optical rails of at least two of the intermediate optical layers in a vertical cross-section of the photonic integrated circuit.