A lithography process is described by a design for a lithographic mask and a description of the lithography configuration, which may include the lithography source, collection/illumination optics, projection optics, resist, and/or subsequent fabrication steps. The actual lithography process uses a lithographic mask fabricated from the mask design, which may be different than the nominal mask design. A mask fabrication model models the process for fabricating the lithographic mask from the mask design. Typically, this is an electron-beam (e-beam) process, which includes e-beam exposure of resist on a mask blank, processing of the exposed resist to form patterned resist, and etching of the mask blank with the patterned resist. The mask fabrication model, usually in conjunction with other process models, is used to estimate a result of the lithography process. Mask correction is then applied to the mask design based on the simulation result.

Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

Disclosed is a method of treating a substrate, the method including: supplying a liquid to the substrate, emitting a laser to the substrate supplied with the liquid to heat the substrate, and emitting imaging light for capturing the substrate to obtain an image of the substrate including a region to which the laser is emitted, in which the laser and the imaging light are emitted to the substrate through a head lens, and a divergence angle of the laser emitted from the head lens and a divergence angle of the imaging light are matched with each other.

Disclosed is a method of treating a substrate, the method including: supplying a liquid to the substrate, emitting a laser to the substrate supplied with the liquid to heat the substrate, and emitting imaging light for capturing the substrate to obtain an image of the substrate including a region to which the laser is emitted, in which the laser and the imaging light are emitted to the substrate through a head lens, and a divergence angle of the laser emitted from the head lens and a divergence angle of the imaging light are matched with each other.

Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.

Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.

An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

A multi-charged particle beam writing apparatus includes a circuit to allocate an additional dose to a position inside a writing target pattern in order to change a first dose distribution by an excessive dose, generated on the target object by applying, in the multi-charged particle beams, an excessive dose defective beam, to a second dose distribution whose center is located inside the writing target pattern and for which beam irradiation canceling out the excessive dose and being in a range of the first dose distribution exists; and a circuit to perform correction by subtracting an increased dose amount, generated at the center of the second dose distribution because of the additional dose being allocated, from a dose with which one of the center of the second dose distribution and a vicinity of the center of the second dose distribution is irradiated.

A multi-charged particle beam writing apparatus includes a circuit to allocate an additional dose to a position inside a writing target pattern in order to change a first dose distribution by an excessive dose, generated on the target object by applying, in the multi-charged particle beams, an excessive dose defective beam, to a second dose distribution whose center is located inside the writing target pattern and for which beam irradiation canceling out the excessive dose and being in a range of the first dose distribution exists; and a circuit to perform correction by subtracting an increased dose amount, generated at the center of the second dose distribution because of the additional dose being allocated, from a dose with which one of the center of the second dose distribution and a vicinity of the center of the second dose distribution is irradiated.