A method and a system for correcting lithography process hotspots based on stress damping adjustment are provided. The method includes: acquiring a mark hotspot of a mask pattern; forming N annuli centered on the mark hotspot from inner to outer on a mask; moving vertexes of the mask pattern located in each annulus by a specific distance in a direction deviating from the mark hotspot and connecting the moved vertexes according to an original connection relationship to acquire an updated layout; verifying electrical characteristics of the updated layout, determining whether a deviation of the electrical characteristics of the updated layout is within a tolerable range, and performing geometric correction to compensate for a deviation of electrical parameters if no is determined and then ending correction, or ending the correction if yes is determined.

Improved methods of manufacturing highly sensitive and selective electrochemical biosensors are provided. The method may comprise washing the nanowell array electrodes of the biosensors with ferricyanide, preferably potassium ferricyanide. The method may also comprise washing the electrodes of the biosensors with methylene blue (i.e., methylthioninium chloride), either in addition to the ferricyanide and/or H2SO4 washing steps, or without the ferricyanide and/or H.sub.2SO.sub.4 washing steps.

The present disclosure relates a lithographic substrate marking tool. The tool includes a first electromagnetic radiation source disposed within a housing and configured to generate a first type of electromagnetic radiation. A radiation guide is configured to provide the first type of electromagnetic radiation to a photosensitive material over a substrate. A second electromagnetic radiation source is disposed within the housing and is configured to generate a second type of electromagnetic radiation that is provided to the photosensitive material.

The invention relates to an optical system and, in particular for characterizing a microlithography mask, comprising a light source for generating light of a wavelength of less than 30 nm, an illumination beam path leading from the light source to an object plane, an imaging beam path leading from the object plane to an image plane and a beam splitter, via which both the illumination beam path and the imaging beam path run.

In a pattern formation method for a semiconductor device fabrication, an original pattern for manufacturing a photomask is acquired, a modified original pattern is obtained by performing an optical proximity correction on the original pattern, a sub-resolution assist feature (SRAF) seed map with respect to the modified original pattern indicating locations where an image quality is improved by an SRAF pattern is obtained, SRAF patterns are placed around the original pattern, the SRAF patterns and the modified original pattern are output as mask data, and the photo mask is manufactured using the mask data.

Embodiments of the invention include methods and structures for controlling developer critical dimension (DCD) variations across a wafer surface. Aspects of the invention include an apparatus having developer tubing and an internal cam. The internal cam is coupled to a fixed axis. A flexible divider is positioned between the developer tubing and the internal cam. The flexible divider is coupled to the internal cam such that rotation of the internal cam about the fixed axis is operable to change an inner diameter of the developer tubing.

A method includes providing a substrate including mandrels of a first material positioned on an underlying layer. Each of the mandrels includes a first sidewall and an opposing second sidewall. The method further includes forming sidewall spacers made of a second material and including a first sidewall spacer abutting each respective first sidewall and a second sidewall spacer abutting each respective second sidewall. The mandrels extend above top surfaces of the sidewall spacers. The method also includes forming first capped sidewall spacers by depositing a third material on the first sidewall spacers without depositing on the second sidewall spacers, forming second capped sidewall spacers by depositing a fourth material on the second sidewall spacers without depositing on the first sidewall spacers, and selectively removing at least one of the first material, the second material, the third material, and the fourth material to uncover an exposed portion of the underlying layer.

The present invention concerns an optical system for spatiotemporally shaping the wavefront of the electric field of a light beam (1) to be projected into a target volume (5), where the propagation axis is axis z, to create 3D patterned illumination in the target volume (5), comprising a pulsed laser source, configured to have an illumination pattern whose transversal surface at the target volume being superior to the diffraction limit of the optical system, at least one intermediate optical element (4) which is a dispersive grating for performing temporal focusing of the light beam (1), located, on the propagation axis (z), where an image of the illumination pattern is formed, for modulating the phase and/or the amplitude of the electric field of the light beam, and a second optical element (3) which is a spatiallight modulator for modulating the phase of the electric field of the input light beam, and for realizing spatiotemporal multiplexing to create 3D patterned illumination in the target volume (5) by replicating the illumination pattern, so as to have several replicated illumination patterns in the target volume (5), and controlling the position with transversal coordinates X, Y and axial coordinate Z of each replicated illumination pattern in the target volume (5).

An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer insulating layer, and a pixel electrode electrically connected to the connection electrode in an upper opening formed in the first dielectric layer and the second dielectric layer.

Methods and arrangement for clamping substrates to a support using adhesive material area disclosed. The method comprises providing a support comprising a first surface defining a plane; applying adhesive material on at least portions of the first surface; and placing the substrate onto the adhesive material, wherein the adhesive material forms a plurality of support locations supporting the substrate. Preferably the adhesive material is cured at least partly during the application of a substantially uniformly distributed force to the substrate in the direction of the support. The arrangements comprise a support comprising a first surface, for supporting the substrate via adhesive material, whereby the first surface defines a plane. Preferably it also comprises an arrangement for providing electromagnetic radiation, thermal energy, and/or a chemical substance to the adhesive material, and an arrangement for providing a substantially uniformly distributed force to the substrate in the direction of the support.