A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.

An example silicon MEMS resonator device includes a support structure, a resonator element with at least one associated eigenmode of vibration, at least one anchor coupling the resonator element to the support structure, at least one driving electrode, and at least one sense electrode. The resonator element is homogeneously doped with N-type or P-type dopants to a doping concentration that causes a closely temperature-compensated mode in which (i) an absolute value of a first order temperature coefficient of frequency of the resonator element is reduced to a first value below a threshold value and (ii) an absolute value of a second order temperature coefficient of frequency of the resonator element is reduced to about zero. Further, a geometry of the resonator element is chosen such that the absolute value of the first order temperature coefficient of frequency is further reduced to a second value smaller than the first value.

The present disclosure relates to a measuring device for measuring a fill level of a material in a container based on time of flight principles, including components that serve to generate, transmit and receive a measurement signal and further serve to convert said measurement signal into an analog intermediate frequency signal having an expected signal frequency within a predetermined frequency range, said intermediate frequency signal including information corresponding to the fill level of the material in the container, wherein an analog to digital converter is provided that serves to subsequently sample the intermediate frequency signal, said analog to digital converter employing a sampling frequency less than the expected signal frequency of intermediate frequency signal.

Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

A timepiece reduces power consumption while maintaining required precision. The timepiece has a frequency divider that frequency divides an oscillation signal and outputs a reference signal; nonvolatile memory that stores information related to a temperature characteristic of the oscillation frequency of the crystal oscillator; multiple registers; a temperature measuring circuit; an evaluation circuit; and a temperature compensation circuit. The temperature compensation circuit reads the information from one of the registers and corrects the reference signal based on the read information and the temperature measurement information when the evaluation circuit determines the information stored in the multiple registers is the same; and when the evaluation circuit determines the information stored in the multiple registers is different, reads the information from the nonvolatile memory, stores the read information in the multiple registers, and corrects the reference signal based on the read information and the temperature measurement information.

A timepiece reduces power consumption while maintaining required precision. The timepiece has a frequency divider that frequency divides an oscillation signal and outputs a reference signal; nonvolatile memory that stores information related to a temperature characteristic of the oscillation frequency of the crystal oscillator; multiple registers; a temperature measuring circuit; an evaluation circuit; and a temperature compensation circuit. The temperature compensation circuit reads the information from one of the registers and corrects the reference signal based on the read information and the temperature measurement information when the evaluation circuit determines the information stored in the multiple registers is the same; and when the evaluation circuit determines the information stored in the multiple registers is different, reads the information from the nonvolatile memory, stores the read information in the multiple registers, and corrects the reference signal based on the read information and the temperature measurement information.

According to some aspects of the present disclosure, an atomic clock and methods of forming and/or using an atomic clock are disclosed. In one embodiment, an atomic clock includes: a light source configured to illuminate a resonance vapor cell; a narrowband optical filter disposed between the light source and the resonance vapor cell and arranged such that light emitted from the light source passes through the narrowband optical filter and illuminates the resonance vapor cell. The resonance vapor cell is configured to emit a signal corresponding to a hyperfine transition frequency in response to illumination from the light source, and a filter cell is disposed between the light source and the resonance vapor cell and configured to generate optical pumping. An optical detector is configured to detect the emitted signal corresponding to the hyperfine transition frequency.

According to some aspects of the present disclosure, an atomic clock and methods of forming and/or using an atomic clock are disclosed. In one embodiment, an atomic clock includes: a light source configured to illuminate a resonance vapor cell; a narrowband optical filter disposed between the light source and the resonance vapor cell and arranged such that light emitted from the light source passes through the narrowband optical filter and illuminates the resonance vapor cell. The resonance vapor cell is configured to emit a signal corresponding to a hyperfine transition frequency in response to illumination from the light source, and a filter cell is disposed between the light source and the resonance vapor cell and configured to generate optical pumping. An optical detector is configured to detect the emitted signal corresponding to the hyperfine transition frequency.

A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.