G05B2219/2205

CONTROL AND MONITORING OF A MACHINE ARRANGEMENT
20220402121 · 2022-12-22 ·

A method for controlling and/or monitoring a machine arrangement having at least one machine, in particular at least one robot, with the aid of a processor arrangement having a plurality of processors each with at least one core. The method includes selecting, in particular temporarily selecting, a first available and at least one further available core on the proviso that these cores are implemented, in particular arranged, on different processors of the processor arrangement, in particular during operation of the machine arrangement and/or on the basis of an updated directory and/or on the basis, in particular as a result, of an ascertained need for redundant processing of process signals; processing process signals redundantly with the aid of these selected cores; and controlling and/or monitoring the machine arrangement on the basis of this processing.

Software defined silicon implementation and management

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement and manage software defined silicon products are disclosed. Example semiconductor devices disclosed herein include circuitry configurable to provide one or more features. Disclosed example semiconductor devices also include a license processor to activate or deactivate at least one of the one or more features based on a license received via a network from a first remote enterprise system. Disclosed example semiconductor devices further include an analytics engine to report telemetry data associated with operation of the semiconductor device to at least one of the first remote enterprise system or a second remote enterprise system, the analytics engine to report the telemetry data in response to activation or deactivation of the at least one of the one or more features based on the license.

Robot Control Method, Robot Control System, And Robot Control Program
20230128011 · 2023-04-27 ·

In a robot system including robots, lower-level control units respectively coupled to the robots and controlling one of the robots, and an upper-level control unit coupled to the lower-level control units and transmitting command information for control of the robots to the lower-level control units, a method of controlling the robots executed by the upper-level control unit is provided. The upper-level control unit includes a processor having a plurality of processor cores. Part of the processor cores of the plurality of processor cores are isolated from the other processor cores. Communication tasks with the lower-level control units are assigned to the isolated part of the processor cores. The isolated part of the processor cores are controlled to execute the communication tasks with the lower-level control units and the command information is transmitted to the lower-level control units. The isolation of the isolated part of the processor cores is released.

Conflict detection circuit for resolving access conflict to peripheral device by multiple virtual machines
09740518 · 2017-08-22 · ·

A system-on-chip device comprises a core supporting a first virtual machine image and a virtual machine monitoring unit capable of communicating with the first virtual machine image. A shareable resource is also provided as well as a conflict detection unit capable of communicating with the virtual machine monitoring unit and the first virtual machine image. The conflict detection unit is arranged to detect, when in use, an access conflict caused by more than one virtual machine image attempting to access initially the shareable resource. The conflict detection unit is arranged to refer, when in use, the access conflict in response to detection thereof to the virtual machine monitoring unit for resolving of the access conflict, thereby handling the access conflict before the virtual machine monitoring unit.

Control device, control method, and non-transitory computer-readable recording medium

A control device executes a step of starting a computation processing of a prediction model; a step of computing a remaining processing time until the computation processing is completed after starting the computation processing of the prediction model; a step of determining whether the determination of the command value based on an output obtained from the prediction model is made within a control timing for controlling the operation of manufacturing by the manufacturing device, on the basis of a computed remaining processing time; and a step of stopping, when it is determined that the determination of the command value is not made within the control timing, the computation processing of the prediction model, determining the command value on the basis of a value of an intermediate result of the computation processing, and controlling the operation of the manufacturing device on the basis of the determined command value.

VEHICLE CONTROL WITH FUNCTIONAL REDUNDANCY
20210341918 · 2021-11-04 ·

A control assembly for an aircraft system according to an example of the present disclosure includes a multi-core processor that has a plurality of cores coupled to a communications module and to an arbitration module. The communications module is operable to communicate information between the plurality of cores and one or more aircraft modules. The plurality of cores include first and second cores operable to concurrently execute a first discrete set of software instructions to generate respective instances of an output. The arbitration module is operable to communicate each and every one of the respective instances to control the one or more aircraft modules. A method of operating an aircraft system is also disclosed.

Method for processing data and programmable logic controller
11775351 · 2023-10-03 · ·

A method for processing data on a programmable logic controller includes a priority with a predetermined priority level assigned to at least one parallel processing section of a program of a master-processor core of a control task. Respective priority levels are inserted into a data structure as the respective master-processor core arrives at the parallel processing section. A parallel-processor core examines whether entries are present in the data structure and processes partial tasks from a work package of the master-processor core the priority level of which ranks first among the entries. A real-time condition of the control task is met by setting executing times of the programs for the master-processor core so that the master-processor core is capable of processing the partial tasks from the work packages without being supported by the parallel-processor core. The master-processor core further processes partial tasks not processed by the at least one parallel-processor core.

Vehicle control with functional redundancy
11815890 · 2023-11-14 · ·

A control assembly for an aircraft system according to an example of the present disclosure includes a multi-core processor that has a plurality of cores coupled to a communications module and to an arbitration module. The communications module is operable to communicate information between the plurality of cores and one or more aircraft modules. The plurality of cores include first and second cores operable to concurrently execute a first discrete set of software instructions to generate respective instances of an output. The arbitration module is operable to communicate each and every one of the respective instances to control the one or more aircraft modules. A method of operating an aircraft system is also disclosed.

Reconfiguration control device
11385977 · 2022-07-12 · ·

In the invention, a problem is solved in which, in order to achieve high performance and high reliability with the conventional multi-core and lockstep core, a redundant lockstep core is necessarily prepared to execute a multi-core program in which an error has occurred, a circuit area increases, and a cost and a power consumption increase. In the invention, a safe operation of a control system is secured by operating a software program operating on a multi-core in which an error has occurred as degenerate software on a core switched from a lockstep operation to a multi-core operation.

SOFTWARE DEFINED SILICON IMPLEMENTATION AND MANAGEMENT

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement and manage software defined silicon products are disclosed. Example semiconductor devices disclosed herein include circuitry configurable to provide one or more features. Disclosed example semiconductor devices also include a license processor to activate or deactivate at least one of the one or more features based on a license received via a network from a first remote enterprise system. Disclosed example semiconductor devices further include an analytics engine to report telemetry data associated with operation of the semiconductor device to at least one of the first remote enterprise system or a second remote enterprise system, the analytics engine to report the telemetry data in response to activation or deactivation of the at least one of the one or more features based on the license.