A PWM controller in a switching mode power supply provides to a power switch a PWM signal determining an ON time and an OFF time. A peak detector detects a voltage peak of a line voltage generated by rectifying an alternating-current input voltage. An OFF-time control unit controls the PWM signal and determines the OFF time in response to a compensation voltage, which is in response to an output voltage of the switching mode power supply. An ON-time control unit controls the PWM signal and determines the ON time in response to the compensation voltage and the voltage peak. The ON-time control unit is configured to make the ON time not less than a minimum ON time, and the minimum ON time is determined in response to the voltage peak.

A power converter includes a buck leg circuit connected between a voltage input of the power converter and ground, a boost leg circuit connected between a voltage output of the power converter and ground, an inductor connected between the buck leg circuit and the boost leg circuit, an error amplifier configured to compare the voltage output of the power converter against a reference voltage to yield a feedback signal, and a control circuit. The control circuit is configured to generate a reference buck ramp configured to be compared against the feedback signal to determine whether to operate the buck leg circuit in buck mode, and to generate a reference boost ramp by superposing a variable boost ramp portion on to the reference buck ramp, the reference boost ramp configured to be compared against the feedback signal to determine whether to operate the boost leg circuit in boost mode.

A power converter includes a buck leg circuit connected between a voltage input of the power converter and ground, a boost leg circuit connected between a voltage output of the power converter and ground, an inductor connected between the buck leg circuit and the boost leg circuit, an error amplifier configured to compare the voltage output of the power converter against a reference voltage to yield a feedback signal, and a control circuit. The control circuit is configured to generate a reference buck ramp configured to be compared against the feedback signal to determine whether to operate the buck leg circuit in buck mode, and to generate a reference boost ramp by superposing a variable boost ramp portion on to the reference buck ramp, the reference boost ramp configured to be compared against the feedback signal to determine whether to operate the boost leg circuit in boost mode.

A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

A PWM controller in a switching mode power supply provides to a power switch a PWM signal determining an ON time and an OFF time. A peak detector detects a voltage peak of a line voltage generated by rectifying an alternating-current input voltage. An OFF-time control unit controls the PWM signal and determines the OFF time in response to a compensation voltage, which is in response to an output voltage of the switching mode power supply. An ON-time control unit controls the PWM signal and determines the ON time in response to the compensation voltage and the voltage peak. The ON-time control unit is configured to make the ON time not less than a minimum ON time, and the minimum ON time is determined in response to the voltage peak.