A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.

A low-dropout regulator (LDO) capable of providing high power-supply rejection ratio (PSRR) and good reverse isolation. The LDO may include a core circuitry and a reverse isolation circuitry. The core circuitry may include a PSRR circuitry coupled to an output node and configured to provide high PSRR at the output node. The reverse isolation circuitry may be configured to provide good reverse isolation at the output node by, for example, providing current in response to ripples at the output node. The reverse isolation circuitry may be configured with bandwidth higher than that of the core circuitry such that it can provide fast transient response. The reverse isolation circuitry may be configurable and/or reconfigurable for a desirable reverse isolation performance. The reverse isolation circuitry may be configurable and/or reconfigurable to trade off between power consumed by the reverse isolation circuitry and a leakage current flowing through the core circuitry.

An apparatus includes a voltage regulator coupled with a first voltage source, which supplies core memory circuitry. A first transistor is coupled between an output of the voltage regulator and input/output (I/O) circuitry. A second transistor is coupled between a second voltage source and the I/O circuitry, the second voltage source to power a set of I/O buffers. Control logic coupled with gates of the first and second transistors is to perform operations including: causing the second transistor to be activated to permit current to flow from the second voltage source to the I/O circuitry; in response to detecting a current draw from the I/O circuitry that satisfies a first threshold criterion, causing the first transistor to be activated; and causing the second transistor to be deactivated over a time interval during which the I/O circuitry is powered by the first voltage source and the second voltage source.

A voltage booster powered by a primary electrical source for providing an adjustable voltage across the load, while a current regulator in series with the load maintains the desired current. When the voltage drop across the current regulator exceeds an upper threshold, the voltage booster's output voltage is reduced to a lower level to reduce the power dissipated by the current regulator, to improve efficiency. When the voltage drop across the current regulator is less than a lower threshold, the voltage booster output is increased to a higher level. In burst mode operation, the voltage booster output alternates between a full voltage and zero voltage, and an optional capacitor provides voltage across the resistive load during discharge. An optional diode can ensure that the capacitor discharges through the load in cases where the voltage booster output is not floating.

Techniques for an on-memory die voltage regulator is disclosed. In the illustrative embodiment, a voltage regulator on a memory die is enabled upon receipt of a memory operation. The illustrative voltage regulator includes an analog controller that controls a shunt current based on a current output voltage of the voltage regulator. The illustrative voltage regulator also includes a digital controller that controls several switches based on the input voltage that control an effective resistance of part of the voltage regulator.

A method and apparatuses for power regulation using an extended current limit are disclosed. The power regulator detects an occurrence of an output current of the regulator exceeding a first current limit, triggers an extended current limit timer based on the detected occurrence, regulates the output current according to a second current limit higher than the first current limit based on a duration of the extended current limit timer, and regulates the output current according to the first current limit based on an expiration of the duration of the extended current limit timer.

A gallium nitride (GaN) transistor-based regulated voltage source has a reference voltage input coupled to a reference voltage. The regulated voltage source also includes an input port and an output port. The regulated voltage source includes a GaN transistor-based voltage regulation path coupling the input port and the output port with at least a GaN regulation transistor with a threshold voltage and that is formed on a substrate. The regulated voltage source also includes a GaN transistor-based voltage compensator having an intermediate GaN transistor that is also formed on the substrate. The GaN transistor-based voltage compensator couples a gate of the GaN regulation transistor to the reference voltage input and introduces a voltage drop between the gate of the GaN regulation transistor and the reference voltage input to compensate for the threshold voltage of the GaN regulation transistor.

A power control device includes: an output voltage controller configured to control an output voltage based on a feedback voltage corresponding to the output voltage; and an overvoltage protector configured to continue or stop the operation of the output voltage controller based on a first detection result of whether the output voltage has exceeded an output voltage threshold value and a second detection result of whether the feedback voltage has fallen to or below a feedback voltage threshold value.

A semiconductor device according to related art has a problem that a clamp voltage that clamps an output voltage cannot adaptively vary in accordance with a power supply voltage, and it is thus not possible to reduce heating of a semiconductor chip to a sufficiently low level. According to one embodiment, a semiconductor device includes a drive circuit (10) that controls on and off of an output transistor (13) and an overvoltage protection circuit (12) that controls a conductive state of the output transistor (13) when an output voltage Vout reaches a clamp voltage, and the overvoltage protection circuit (12) has a circuit structure that sets the clamp voltage to vary in proportion to a power supply voltage VDD.

An amplifier circuit includes an amplifier, a resistor, and an adaptive bias circuit. The amplifier includes an output and a tail input. The amplifier is configured to generate an output signal representative of a difference of a first input signal and a second input signal. The resistor is coupled to the output of the amplifier. The resistor is configured to lower an output resistance of the amplifier. The adaptive bias circuit is coupled between the output of the amplifier and the tail input of the amplifier. The adaptive bias circuit is configured to generate a detection current based on the output signal, and provide the detection current to the tail input of the amplifier to increase the gain of the amplifier based on the output signal.