An approach to obtain low latency association of the audio clock in a smartphone with an incoming RF message is to use an interrupt driven routine, where the receipt of the RF message preamble generates an interrupt that reads the audio clock counter since the start of the audio session. In some embodiments such an approach may be implemented on the specialized processing cores found in smartphones that control RF communication, sensor or audio processing.

An approach to obtain low latency association of the audio clock in a smartphone with an incoming RF message is to use an interrupt driven routine, where the receipt of the RF message preamble generates an interrupt that reads the audio clock counter since the start of the audio session. In some embodiments such an approach may be implemented on the specialized processing cores found in smartphones that control RF communication, sensor or audio processing.

A problem to be solved by the present invention is, in a computer system, to reduce processing delay from wait times which occur in timer access. According to the present invention, using either a CPU core (hereinafter “processing core”) other than a CPU core which executes an application, or a DMA device, a latest timer value is always transferred from a timer device to a primary storage device. The processing core reads the transferred value upon the primary storage device instead of accessing a register of the timer device, thereby avoiding a wait which occurs when directly reading the timer value of the timer device. The transfer of the value is carried out asynchronously from the processing of the processing core, thus obviating the need for the processing core to wait for the completion of the transfer. Accordingly, it is also unnecessary for the processing core to process an interrupt or a notification from another CPU core or the DMA device.

A problem to be solved by the present invention is, in a computer system, to reduce processing delay from wait times which occur in timer access. According to the present invention, using either a CPU core (hereinafter “processing core”) other than a CPU core which executes an application, or a DMA device, a latest timer value is always transferred from a timer device to a primary storage device. The processing core reads the transferred value upon the primary storage device instead of accessing a register of the timer device, thereby avoiding a wait which occurs when directly reading the timer value of the timer device. The transfer of the value is carried out asynchronously from the processing of the processing core, thus obviating the need for the processing core to wait for the completion of the transfer. Accordingly, it is also unnecessary for the processing core to process an interrupt or a notification from another CPU core or the DMA device.

Systems and methods for providing a synthetic track to observation devices are provided. In one embodiment, a method can include determining a location range and a time range for a synthetic track to be created by a plurality of platforms. The method can further include determining an emission location and an emission time for each of the platforms of the plurality of platforms based, at least in part, on the location range and the time range. The method can include sending a set of data to each of the plurality of platforms, each respective set of data indicating the emission location and the emission time at which the respective platform is to generate the emission to create the synthetic track.

Systems and methods for providing a synthetic track to observation devices are provided. In one embodiment, a method can include determining a location range and a time range for a synthetic track to be created by a plurality of platforms. The method can further include determining an emission location and an emission time for each of the platforms of the plurality of platforms based, at least in part, on the location range and the time range. The method can include sending a set of data to each of the plurality of platforms, each respective set of data indicating the emission location and the emission time at which the respective platform is to generate the emission to create the synthetic track.

A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.

An apparatus and method for synchronizing a triggered system to a triggering system by tracking the timing of rising and falling edges of a clock signal at the triggered system and using the tracked timing values for phase shift adjustment of a time base at the triggered systems.

In an embodiment a method includes generating a low-frequency clock signal having a first frequency, in a standby mode and in a run mode of the CPU, generating a high-frequency clock signal having a second frequency higher than the first frequency, in the run mode, updating a value of the reference time base at each period of the low-frequency clock signal in the standby mode, and accessing the counter register with the high-frequency clock signal in the run mode.