An information handling system sets up at power-on self-test, a system management interrupt based on a trap on an input/output port used for a real-time clock and detects at runtime, an operation on the input/output port. In response to detecting the operation on the input/output port, generates the system management interrupt based on the trap on the input/output port. In addition, the information handling system handles the system management interrupt by emulating the real-time clock according to the operation on the input/output port that includes determining a register that is mapped to an index associated with the operation and accessing the register and executing a function associated with the register.

An information handling system sets up at power-on self-test, a system management interrupt based on a trap on an input/output port used for a real-time clock and detects at runtime, an operation on the input/output port. In response to detecting the operation on the input/output port, generates the system management interrupt based on the trap on the input/output port. In addition, the information handling system handles the system management interrupt by emulating the real-time clock according to the operation on the input/output port that includes determining a register that is mapped to an index associated with the operation and accessing the register and executing a function associated with the register.

Systems and apparatuses include a circuit structured to communicate with a real-time-clock battery and to selectively communicate with a vehicle battery, inhibit communication between the real-time-clock battery and a controller when a first voltage is received from the vehicle battery, and provide a communication from the real-time-clock battery to the controller when the first voltage is not received.

Systems and apparatuses include a circuit structured to communicate with a real-time-clock battery and to selectively communicate with a vehicle battery, inhibit communication between the real-time-clock battery and a controller when a first voltage is received from the vehicle battery, and provide a communication from the real-time-clock battery to the controller when the first voltage is not received.

The invention relates to a method for providing a fault-tolerant global time via a time server in a distributed real-time computer system, wherein the time server comprises four components which are connected to one another via a bi-directional communication channel. At a priori defined periodic, internal synchronization times, each of the four components transmits an internal synchronization message, which is simultaneously transmitted to the other three components, from which each internal computer of a component determines a correction term for the tick counter contained in its component and corrects the reading of the local tick counter by this correction term.

In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

A sensing apparatuses includes a sensor, a processing circuit that acquires sensor output information from the sensor, a communication circuit that transmits transmission information corresponding to the sensor output information, and a clocking circuit that generates time information. The communication circuit receives time information for correction before the processing circuit starts acquiring the sensor output information. The clocking circuit corrects the time information based on the time information for correction received by the communication circuit. The processing circuit starts acquiring the sensor output information based on the corrected time information.

A device implementing a real time clock integrated module for outputting data indicating a time-of-day. The real time clock integrated module includes: a high-precision oscillator or atomic clock having an accuracy of 50 ppb (parts per billion) or better; a timing circuit for generating time-of-day data according to a clock signal outputted from the oscillator or atomic clock; a power source allowing the timing circuit to maintain time when the device is powered off. The timing circuit includes a real time clock and a logic device storing a timestamp. The timing circuit is configured when the device is powered off to update the timestamp value based on the oscillator or atomic clock and to generate a time reference signal and to provide to the device the updated timestamp value and the time reference signal that the device can use as a time reference once the device is powered up again.

An electronic device is disclosed and includes a display and at least one processor operatively connected with the display. The at least one processor is configured to, when an application is executed, display an execution window corresponding to the application on the display, display the execution window, as a first shape of execution window, on at least a portion of the display, in response to a background switch request for the application, identify a state of the application while displaying the first shape of execution window, and switch the first shape of execution window into a second shape of execution window according to the state of the application.