The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) on a printed circuit board (PCB), and connecting the SoC to a storage unit; enabling the SoC to read a boot code from the storage unit, and executing the boot code to perform an AVS scanning operation on the SoC to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC to establish an AVS look-up table; and storing the AVS look-up table into the SoC or the storage unit.

Systems, apparatus, and methods that control power consumption in a processor are disclosed. One system apparatus, and method includes a processor that operates in at least a first power control mode including a first power amount and a second power control mode including a second power amount lower than the first power amount and a power control device. The power control device is configured to control power consumption in the processor, change a power control mode of the processor to the first power control mode in response to a first excess time period in which the power consumption of the processor exceeds a first reference power for a first period of time, and change the power control mode of the processor to the second power control mode in response to a second period of time in which the power consumption is less than or equal to a second reference power.

Aspects of the present disclosure control aging of a signal path in an idle mode to mitigate aging. In one example, an input of the signal path is alternately parked low and high over multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is parked high or low during each idle period based on an aging pattern.

A computer may be provided on a mining machine comprising a mother board, a power supply in operable communication with the mother board, an input/output interface in communication with the mother board, and a plurality of hash boards each in communication with the mother board and comprising a plurality of mining chips. The computer may execute instructions that cause the computer to perform establishing communication with an external device, retrieving at least one profit variable from the external device, calculating an estimated profitability of a first mining chip based on the profit variable, and adjusting a chip voltage supplied to the first mining chip and adjusting a chip frequency of the first mining chip to maximize the estimated profitability. Alternatively, the instructions may cause the computer to adjust the chip voltage and the chip frequency to maintain a temperature within a predetermined range.

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for training a deep neural network. One of the methods includes generating a plurality of feature vectors that each model a different portion of an audio waveform, generating a first posterior probability vector for a first feature vector using a first neural network, determining whether one of the scores in the first posterior probability vector satisfies a first threshold value, generating a second posterior probability vector for each subsequent feature vector using a second neural network, wherein the second neural network is trained to identify the same key words and key phrases and includes more inner layer nodes than the first neural network, and determining whether one of the scores in the second posterior probability vector satisfies a second threshold value.

An information processing apparatus comprises: an arithmetic unit configured to perform arithmetic operation processing using a hierarchical network; a storage unit configured to store input data inputted to the arithmetic unit and output data outputted from the arithmetic unit; a transmission unit configured to transmit to the arithmetic unit the input data stored in the storage unit; a reception unit configured to receive and store in the storage unit the output data from the arithmetic unit; and a control unit configured to, in a case where the input data cannot be transmitted from the storage unit to the arithmetic unit, control supply of an operation clock to the transmission unit based on network information that indicates a structure of the hierarchical network.

An information processing apparatus comprises: an arithmetic unit configured to perform arithmetic operation processing using a hierarchical network; a storage unit configured to store input data inputted to the arithmetic unit and output data outputted from the arithmetic unit; a transmission unit configured to transmit to the arithmetic unit the input data stored in the storage unit; a reception unit configured to receive and store in the storage unit the output data from the arithmetic unit; and a control unit configured to, in a case where the input data cannot be transmitted from the storage unit to the arithmetic unit, control supply of an operation clock to the transmission unit based on network information that indicates a structure of the hierarchical network.

A power management controller is disclosed. Broadly speaking, the controller may, in response to receiving a timing signal, monitor a temperature of an integrated circuit including multiple processor clusters. The controller may generate a comparison of the temperature and a threshold value, and in response to a determination that the comparison indicates that the temperature is less than the threshold value, transition a particular processor cluster to a new power state.