Aspects of a storage device including a controller memory, a die memory, and a plurality of accumulators corresponding to individual DQs are provided for accelerated DQ training and error detection. A controller stores first data in the controller memory, transfers second data to the die memory over an n-bit bus, and receives n bits of the second data from the die memory based on a DQS. The controller then compares n bits of the first data with n bits of the second data to produce n bit results received into respective accumulators, and the controller simultaneously updates different accumulators in response to bit mismatches. During DQ training, if an accumulator value meets a mismatch threshold, the controller modifies a DQS-DQ timing accordingly. During error detection of a read scrambled page, if an accumulator value does not meet an entropy threshold, the controller identifies an error associated with the page.

Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.

A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.

Provided are an apparatus, memory device, and method to determine error location polynomial coefficients to provide to bit correction logic instances to decode bits of a codeword. A memory controller for a memory includes coefficient generating logic to receive as input a plurality of syndrome values to generate a plurality of coefficients for an error locator polynomial. A plurality of instances of bit correction logic, one instance for each bit of bits to correct in a codeword for a block in the memory array to decode. Each instance of bit correction logic is to receive as input the coefficients for the error locator polynomial and elements for the bit to correct from a decoder alphabet to determine whether to correct the bit and output as a decoded bit the bit or a corrected bit to include in a decoded codeword.

The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.

Memory with an error correction circuit includes: a first error correction circuit performing error correction on first partial data to generate first partial write data or first partial read data; and a second error correction circuit performing error correction on second partial data to generate second partial write data or second partial read data. In a write mode, a plurality of sensing drive circuits respectively receive a plurality of first partial write bits of the first partial write data and a plurality of second partial write bits of the second partial write data, and each sensing drive circuit combines the first partial write bits with the corresponding second partial write bits and writes them to corresponding memory cell columns; in a read mode, the sensing driving circuits respectively sense stored data in the memory cell columns to generate a plurality of first partial read data and second partial read data.

Memory with an error correction circuit includes: a first error correction circuit performing error correction on first partial data to generate first partial write data or first partial read data; and a second error correction circuit performing error correction on second partial data to generate second partial write data or second partial read data. In a write mode, a plurality of sensing drive circuits respectively receive a plurality of first partial write bits of the first partial write data and a plurality of second partial write bits of the second partial write data, and each sensing drive circuit combines the first partial write bits with the corresponding second partial write bits and writes them to corresponding memory cell columns; in a read mode, the sensing driving circuits respectively sense stored data in the memory cell columns to generate a plurality of first partial read data and second partial read data.

The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.

Various implementations described herein relate to systems and methods for performing error correction in a flash memory device by determining suggested corrections by decoding a codeword. In addition, whether a first set of the suggested corrections obtained based on a first component code of the plurality of component codes agree with a second set of the suggested corrections obtained based on a second component code of the plurality of component codes is determined. One of accepting the first set of the suggested corrections or rejecting the first set of the suggested corrections is selected based on whether the first set of the suggested corrections and the second set of the suggested corrections agree.