Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

A computer-implemented method, in which an access request in relation to data is received. There is Error Correcting Code (ECC) data relating to the data, and the ECC data is configured to enable correction of multiple-bit errors spanning up to a predetermined number of consecutive bits of the data. The ECC data is configured to enable correction of multiple-bit errors spanning up to a predetermined number of consecutive bits of the data. A first integrity verification verifies the integrity of at least the data. If the first integrity verification procedure fails, an error analysis procedure is performed based on the data and the ECC data. Responsive to generation of corrected data by the error analysis procedure, a second integrity verification verifies the integrity of the corrected data. If the second integrity verification is successful, the access request is allowed using the corrected data.

A method begins by a first computing device determining a routing plan to route a set of encoded data slices from the first computing device to a second computing device via a plurality of network paths of a communications network. The method continues with the second computing device receiving encoded data slices via one or more network paths. When the second computing device receives a decode threshold number of encoded data slices, the method continues with the second computing device sending a message to the communications network indicating receipt of the decode threshold number of encoded data slices. The method continues with a relay unit determining whether the relay unit is in possession of a not-yet delivered encoded data slice. When the relay unit is in possession of the not-yet delivered encoded data slice, the method continues with the relay unit ceasing forwarding of the not-yet delivered encoded data slice.

A configuration structure and method of a block memory. The configuration structure includes a first port, a second port, an ECC module, and an FIFO module; the ECC module includes an ECC encoder and an ECC decoder; the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock synchronous or asynchronous with and the write clock of the block memory. The read width and the write width of the block memory can be independently configured, and the block memory has built-in an ECC function and a FIFO function, and can be cascaded to a block memory with larger storage space without consuming additional logic resource.

Aspects of a storage device including a controller memory, a die memory, and a plurality of accumulators corresponding to individual DQs are provided for accelerated DQ training and error detection. A controller stores first data in the controller memory, transfers second data to the die memory over an n-bit bus, and receives n bits of the second data from the die memory based on a DQS. The controller then compares n bits of the first data with n bits of the second data to produce n bit results received into respective accumulators, and the controller simultaneously updates different accumulators in response to bit mismatches. During DQ training, if an accumulator value meets a mismatch threshold, the controller modifies a DQS-DQ timing accordingly. During error detection of a read scrambled page, if an accumulator value does not meet an entropy threshold, the controller identifies an error associated with the page.

Various implementations described herein relate to systems and methods for performing error correction in a flash memory device by determining suggested corrections by decoding a codeword. In addition, whether a first set of the suggested corrections obtained based on a first component code of the plurality of component codes agree with a second set of the suggested corrections obtained based on a second component code of the plurality of component codes is determined. One of accepting the first set of the suggested corrections or rejecting the first set of the suggested corrections is selected based on whether the first set of the suggested corrections and the second set of the suggested corrections agree.

A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.

Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

Address translation of host commands to access host data stored in memory devices that provides a chip kill capability not only involves locating where the host data is stored, but also involves locating where parity data striped with the host data is stored. In locating where the parity data is stored, the address translation can be performed with logical (e.g., arithmetic) operations.