A fault tolerant quantum error correction protocol is implemented for a surface code comprising Gottesman Kitaev Preskill (GKP) qubits. Analog information is determined when measuring position or momentum shifts, wherein the analog information indicates a closeness of the shift to a decision boundary. The analog information may further be used to determine confidence values for error corrected measurements from the GKP qubits of the surface code.

A fault tolerant quantum error correction protocol is implemented for a surface code comprising Gottesman Kitaev Preskill (GKP) qubits. Analog information is determined when measuring position or momentum shifts, wherein the analog information indicates a closeness of the shift to a decision boundary. The analog information is further used to determine confidence values for error corrected measurements from the GKP qubits of the surface code. These confidence values are used to dynamically determine edge weights in a matching graph used to decode syndrome measurements of the surface code, wherein the confidence values are obtained using a maximum-likelihood decoding protocol for two-qubit gates. Also, a three-level ancilla is used to more reliably squeeze the GKP qunaught states.

Examples relate to a Low-Density Parity-Check Code (LDPC) decoder apparatus or device, to an LDPC decoder system and to corresponding methods and computer programs. The LDPC decoder apparatus comprises input circuitry and processing circuitry. The processing circuitry is configured to obtain a syndrome of a codeword via the input circuitry. The processing circuitry is configured to perform LDPC iterative decoding using the obtained syndrome, wherein the changes to be applied to the codeword due to the LDPC iterative decoding are recorded by applying the changes to a surrogate codeword. The processing circuitry is configured to record changes to be applied to the codeword due to the LDPC iterative decoding by storing the surrogate codeword in a memory structure.

Introduced here is a technique to detect and/or correct errors in computation. The ability to correct errors in computation can increase the speed of the processor, reduce the power consumption of the processor, and reduce the distance between the transistors within the processor because the errors thus generated can be detected and corrected. In one embodiment, an error correcting module, running either in software or in hardware, can detect an error in matrix multiplication, by calculating an expected sum of all elements in the resulting matrix, and an actual sum of all elements in the resulting matrix. When there is a difference between the expected sum and the resulting sum, the error correcting module detects an error. In another embodiment, in addition to detecting the error, the error correcting module can determine the location and the magnitude of the error, thus correcting the erroneous computation.

A storage system generates a low-density parity check (LDPC) code from a plurality of subcodes. The storage system stores each subcode in a different page of a word line in the memory. The subcode can be stored in one plane in the memory or across multiple planes. When the subcodes are stored across multiple planes, they can be stored in a checkboard pattern.

Introduced here is a technique to detect and/or correct errors in computation. The ability to correct errors in computation can increase the speed of the processor, reduce the power consumption of the processor, and reduce the distance between the transistors within the processor because the errors thus generated can be detected and corrected. In one embodiment, an error correcting module, running either in software or in hardware, can detect an error in matrix multiplication, by calculating an expected sum of all elements in the resulting matrix, and an actual sum of all elements in the resulting matrix. When there is a difference between the expected sum and the resulting sum, the error correcting module detects an error. In another embodiment, in addition to detecting the error, the error correcting module can determine the location and the magnitude of the error, thus correcting the erroneous computation.

A storage system generates a low-density parity check (LDPC) code from a plurality of subcodes. The storage system stores each subcode in a different page of a word line in the memory. The subcode can be stored in one plane in the memory or across multiple planes. When the subcodes are stored across multiple planes, they can be stored in a checkboard pattern.

A method includes generating an extended result from a first operation circuitry having a result register bit width greater than a bus width associated with a residue check path of a second operation circuitry associated with a floating point unit. An extended result residue less a first portion residue of the extended result received from the residue check path is stored as a first partial result residue. The first partial result residue is compared with a first result residue of the second operation circuitry. The extended result residue less both the first partial result residue and a second portion residue of the extended result received from the residue check path as a second partial result residue is compared with a second result residue of the second operation circuitry.

A fault tolerant quantum error correction protocol is implemented for a surface code comprising Gottesman Kitaev Preskill (GKP) qubits. Analog information is determined when measuring position or momentum shifts, wherein the analog information indicates a closeness of the shift to a decision boundary. The analog information is further used to determine confidence values for error corrected measurements from the GKP qubits of the surface code. These confidence values are used to dynamically determine edge weights in a matching graph used to decode syndrome measurements of the surface code, wherein the confidence values are obtained using a maximum-likelihood decoding protocol for two-qubit gates. Space-time correlated edges and other edges are included in the matching graph and weighted based at least in part on confidence values for qubits forming the respective edges.

Methods, systems, and apparatus for detecting single event effects. The system includes a first-modulus digital logic unit and a second-modulus digital logic unit each configured to reduce one or more operands by a respective modulus, apply an arithmetic compute logic to the reduced operands to produce a respective compute output, and reduce the respective compute output by their respective modulus. The system includes a kernel digital logic unit configured to apply the arithmetic compute logic to the operands to produce a kernel compute output, output the kernel compute output reduced by the first modulus, and output the kernel compute output reduced by the second modulus. The system includes a detector configured to detect a single event effect based on the reduced first compute output, the kernel compute output reduced by the first modulus, the reduced second compute output, and the kernel compute output reduced by the second modulus.