The invention relates to a method for providing a fault-tolerant global time via a time server in a distributed real-time computer system, wherein the time server comprises four components which are connected to one another via a bi-directional communication channel. At a priori defined periodic, internal synchronization times, each of the four components transmits an internal synchronization message, which is simultaneously transmitted to the other three components, from which each internal computer of a component determines a correction term for the tick counter contained in its component and corrects the reading of the local tick counter by this correction term.

One example method includes performing failure recovery operations in a computing system using matrix clocks. Each node or process in a computing system is associated with a matrix clock. As events and transitions occur in the computing systems, the matrix clocks are updated. The matrix clocks provide a chronological and casual view of the computing system and allow a recovery line to be determined in the event of system failure.

The systems and methods described herein provide the ability to detect a clocking element fault within an IC device and switch to an alternate clock. In response to detection of a fault in a phase-lock-loop (PLL) clocking element, the device may switch to an alternate clock so that error reporting logic can make forward progress on generating error message. The error message may be generated within an Intellectual Property (IP) cores (e.g., IP blocks), and may send the error message from the IP core to a system-on-a-chip (SOC), such as through an SOC Functional Safety (FuSA) error reporting infrastructure. In various examples, the clocking error may also be output to a hardware SOC pin, such as to provide a redundant path for error indication.

An integrated circuit (IC) includes a first circuit including a timer for receiving an adjustable clock signal. Responsive to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than the reference clock, the first circuit adjusts the frequency of the adjustable clock to a frequency higher than the lower frequency, and then receives an elapsed time associated with the non-operational power state and starts the timer using an adjusted timer value.

A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

The present disclosure relates to clock switching methods, devices, and storage medium. In one example method, a slave clock device may monitor a working status of a master clock device, and sends first indication information when discovering that the master clock device is in a faulty state, so that a communications device synchronizes with a system clock of the communications device based on time information of the slave clock device.

In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.

A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

A frequency converter has a control unit. The control unit has: a serial control unit interface, a control unit clock pulse generator for generating a control unit clock pulse, wherein data are transmitted via the serial control unit interface depending on the control unit clock pulse, and a control unit processor which is designed to define at least one control parameter depending on at least one actual value. The frequency converter furthermore has a power unit which has a data connection to the control unit and has: a number of power semiconductors, a power unit clock pulse generator for generating an adjustable power unit clock pulse, a serial power unit interface which is connectable to the control unit interface in order to set up a data connection, a clock pulse generator adjustment unit which has a signal connection to the power unit interface and which is designed to adjust the power unit clock pulse depending on signals which are received by the power unit on the power unit interface, a power unit processor which is designed to control the power semiconductors depending on the control parameter and the power unit clock pulse, and at least one sensor unit which is designed to determine the at least one actual value, wherein the control unit is designed to transmit the at least one control parameter via the control unit interface to the power unit, and wherein the power unit is designed to transmit the at least one actual value via the power unit interface to the control unit.

The disclosure relates to an apparatus and method for false pass detection in lockstep dual processing core systems, triple modular redundancy (TMR) systems, or other redundant processing systems. A false pass occurs when two processing cores generate matching data outputs, both of which are in error. A false pass may occur when the processing core are both subjected to substantially the same adverse condition, such as a supply voltage drop or a sudden temperature change or gradient. The apparatus includes processing cores configured to generate first and second data outputs and first and second timing violation signals. A voter-comparator validates the first and second data outputs if they match and the first and second timing violation signals indicate no timing violations. Otherwise, the voter comparator invalidates the first and second data outputs. Validated data outputs are used for performing additional operations, and invalidated data outputs may be discarded.