A method is provided for a hyper-converged storage-compute system to implement an active-active failover architecture for providing Internet Small Computer System Interface (iSCSI) target service. The method intelligently selects multiple hosts to become storage nodes that process iSCSI input/output (I/O) for a target. The method further enables iSCSI persistent reservation (PR) to handle iSCSI I/Os from multiple initiators.

Techniques including receiving a first control value, starting a timeout counter based on receiving the first control value, receiving a second control value, determining whether the second control value is received before the timeout counter expires, and based on the determination that the second control value is received before the timeout counter expires: determining whether the first control value is the same as the second control value, and loading the first control value into a set of control registers based on the determination that the first control value is the same as the second control value.

Described is a differential data bus system which maintains error free communication despite faults in one of the data bus lines.

A circuit includes a primary register region and a primary shadow register; a secondary register region and a secondary shadow register; and a safety controller having multiple states. The safety controller transitions to a first write state when a first write signal to write a first value to the primary register region is detected, and copies the first value written to the primary register region to the primary shadow register; transitions to a second write state when a second write signal to write a second value to the secondary register region is detected within a set amount of time of detection of the first write signal, and in the second write state, copies the second value written to the secondary register region to the secondary shadow register; transitions to a compare state to receive a comparison signal indicating whether the first value is the same as the second value; and transitions to an update state when the first value is the same as the second value.

Examples of techniques for hardware assisted data protection are disclosed. In one example implementation according to aspects of the present disclosure, a method may include receiving a read data record comprising at least one memory write, the read data record having an associated cyclic redundancy check (CRC). The method may further include calculating, by a hardware module, an expected CRC for the read data record. Additionally, the method may include comparing the expected CRC to a known CRC stored in a known CRC data store. Finally, the method may include authenticating the read data record when the expected CRC matches a corresponding known CRC.

A redundancy device which is configured to communicate with a redundancy opposite device and perform a redundancy execution, the redundancy device includes receivers configured to receive individually HB signals transmitted from the redundancy opposite device, a calculator configured to calculate a number of normal communication paths among communication paths of the HB signals based on a reception result of the receivers, a comparator configured to compare a calculation result of the calculator with a predetermined threshold value, and a changer configured to change the redundancy device from a standby state to an operating state, or change the redundancy device from the standby state to a not-standby state in which the redundancy execution is released, based on the calculation result of the calculator and a comparison result of the comparator.

A monitoring device is mounted in each of a plurality of operational systems constituting a fault-tolerant system. The plurality of operational systems have an identical configuration including a processor system. The monitoring device includes a processor. The processor executes instruction to read data from a predetermined storage area in a memory of an accessory device to be monitored, connected to the processor system. The processor further executes instruction to compare the read data with reference data held in advance. The processor further executes instruction to separate the processor system connected to the accessory device to be monitored from the fault-tolerant system when the read data is different from the reference data.

An input/output (I/O) device for a distributed modular I/O system includes a base adapted to be connected to an associated support structure. A terminal block is connected to the base and includes a plurality of wiring connections adapted to be connected to field wiring of an associated controlled system. The I/O device further includes first and second I/O modules each including a plurality of removable single-channel I/O submodules that are each releasably connected to the base and each configured for a select I/O operation for input and output of data relative to the associated controlled system. One or more pairs of the single-channel I/O submodules can be configured to be redundant within or between the first and second I/O modules. Each of the single-channel I/O submodules is operatively connected to wiring connections of the terminal block through the base. The I/O device further includes first and second network switches connected to the base. The first and second network switches are adapted to be respectively connected to first and second backplane circuits. The I/O device further includes first and second system modules connected to the base and each respectively connected to both of the first and second network switches. The first and second system modules are also each respectively operatively connected to all of the removable single-channel I/O submodules of both of the first and second I/O modules such that the first and second system modules control communication of I/O data between the first and second network switches and the single-channel I/O submodules.

A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.

The present invention provides a microcontroller which can continue operation even at the time of a failure without making a memory redundant to suppress increase in chip area. The microcontroller includes three or more processors executing the same process in parallel and a storage device. The storage device includes a memory mat having a storage region which is not redundant, an address selection part, a data output part, and a failure recovery part. The address selection part selects a storage region in the memory mat on the basis of three or more addresses issued at the time of an access by the processors. The data output part reads data from the storage region in the memory mat selected by the address selection part. The failure recovery part corrects or masks a failure of predetermined number or less which occurs in the memory mat, the address selection part, and the data output part.