G06F11/1645

VERIFYING PROCESSING LOGIC OF A GRAPHICS PROCESSING UNIT
20230043280 · 2023-02-09 ·

A method of verifying processing logic of a graphics processing unit receives a test task including a predefined set of instructions for execution on the graphics processing unit, the predefined set of instructions being configured to perform a predetermined set of operations on the graphics processing unit when executed for predefined input data. In a test phase, the test task is processed by executing the predefined set of instructions for the predefined input data first and second times at the graphics processing unit so as to, respectively, generate first and second outputs. A fault signal is raised if the first and second outputs do not match.

DEVICE FOR CONTROLLING AN AUTOMATED DRIVING OPERATION OF A VEHICLE
20220396276 · 2022-12-15 ·

A device for controlling an automated driving operation of a vehicle may have at least two brake systems, at least two steering systems, an engine controller, a first automated drive controller, a second automated drive controller, a surroundings sensor assembly, and inertial sensors. A third automated drive controller at least controls the vehicle into a standstill. The device is configured such that the automated driving operation is initiated and/or maintained only when the brake systems, steering systems, and at least two of the automated drive controllers are functional and such that the automated driving operation is interrupted if only one of the automated drive controllers is functional and/or if one of the brake systems and/or steering systems is not functional and/or if the engine controller is not functional, in which case the still functional automated drive controller assumes control of the vehicle and guides the vehicle into a standstill.

Secure system that includes driving related systems

A system that may include multiple driving related systems that are configured to perform driving related operations; a selection module; multiple fault collection and management units that are configured to monitor statuses of the multiple driving related systems and to report, to the selection module, at least one out of (a) an occurrence of at least one critical fault, (b) an absence of at least one critical fault, (c) an occurrence of at least one non-critical fault, and (d) an absence of at least one non-critical fault; and wherein the selection module is configured to respond to the report by performing at least one out of: (i) reset at least one entity out of the multiple fault collection and management units and the multiple driving related systems; and (ii) select data outputted from a driving related systems.

LOCKSTEP COMPARATORS AND RELATED METHODS

Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

Error detection circuit

A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.

SECURE SYSTEM THAT INCLUDES DRIVING RELATED SYSTEMS

A system that may include multiple driving related systems that are configured to perform driving related operations; a selection module; multiple fault collection and management units that are configured to monitor statuses of the multiple driving related systems and to report, to the selection module, at least one out of (a) an occurrence of at least one critical fault, (b) an absence of at least one critical fault, (c) an occurrence of at least one non-critical fault, and (d) an absence of at least one non-critical fault; and wherein the selection module is configured to respond to the report by performing at least one out of: (i) reset at least one entity out of the multiple fault collection and management units and the multiple driving related systems; and (ii) select data outputted from a driving related systems.

Information processing system and method
09811404 · 2017-11-07 · ·

An information processing system includes: a first system that includes a group of arithmetic units, a controller, and an external device; and a second system configured to execute calculation which is the same as calculation executed in the first system and compare calculation results to each other, wherein the controller is configured to: stop a plurality of arithmetic units when it is detected that an output request to the external device is output from one or more arithmetic units among the plurality of arithmetic units that execute first calculation in the group of arithmetic units, the plurality of arithmetic units including one or more arithmetic units that does not output the output request, transmit first comparison target data including a value output in response to the output request to the second system, and instruct the stopped one or more arithmetic units to execute second calculation.

Electronic fault detection unit
09823983 · 2017-11-21 · ·

An electronic fault detection unit is provided that has a first register, a second register, a comparator circuit, and a timer circuit. The first and second register can be written from a first software portion, and a second software portion, respectively. The comparator circuit is arranged to detect that both the first and second register have been written, verify a relationship between first data written to the first register and second data written to the second register, and signal a fault upon said verification failing. The timer circuit is arranged to signal a fault if said verification of the comparator circuit does not occur within a time limit.

Fault tolerant server
09785524 · 2017-10-10 · ·

A fault tolerant server according to the present invention configured to duplicate information processing by an online subsystem and an offline subsystem, the fault tolerant server operates to: execute entire copy processing for copying all data being stored in the memory of the online subsystem into the memory of the offline subsystem without stopping execution of information processing by the processor of the online subsystem, before start of duplication; detect data, the data satisfying a criterion indicating that content of data is changed during the entire copy processing, among data being stored in the memory of the online subsystem; and copy the detected data from the memory of the online subsystem into the memory of the offline subsystem.

Semiconductor device with output data selection of lockstepped computing elements based on diagnostic information

Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.