A residue-based error checking mechanism is provided for checking for error in a shift operation of a shifter. The checking includes: partitioning an input vector into the shifter into one or more bit groups of bit width W; generating a predicted residue on the input vector being shifted, the generating including masking out any bit group of bit width W fully shifted out by the shift operation from contributing to the predicted residue, and the generating accounting for any bits of a bit group of the input vector partially shifted out by the shift operation; generating a result residue on a result vector of the shift operation; and comparing the result residue with the predicted residue to check for an error in the result vector of the shift operation.

The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.

A processor is described that includes a plurality of compute units. One or more test pattern generators generates one or more test patterns and inputs the one or more test patterns into one or more of the plurality of compute units during testing, which testing includes processing of the one or more test patterns by one or more of the plurality of compute units. One or more control and sequencing logic units identifies an idle period during normal use of the processor in which a compute unit of the plurality of compute units is idle. The one or more control and sequencing units controls the test pattern generator to generate and input the one or more test patterns to the idle compute unit and controls the compute unit to process the one or more test patterns during the idle period. One or more comparators compares a result of testing with an expected result of testing to determine if the compute unit is functioning correctly.

A processor is described that includes a plurality of compute units. One or more test pattern generators generates one or more test patterns and inputs the one or more test patterns into one or more of the plurality of compute units during testing, which testing includes processing of the one or more test patterns by one or more of the plurality of compute units. One or more control and sequencing logic units identifies an idle period during normal use of the processor in which a compute unit of the plurality of compute units is idle. The one or more control and sequencing units controls the test pattern generator to generate and input the one or more test patterns to the idle compute unit and controls the compute unit to process the one or more test patterns during the idle period. One or more comparators compares a result of testing with an expected result of testing to determine if the compute unit is functioning correctly.

A method includes generating an extended result from a first operation circuitry having a result register bit width greater than a bus width associated with a residue check path of a second operation circuitry associated with a floating point unit. An extended result residue less a first portion residue of the extended result received from the residue check path is stored as a first partial result residue. The first partial result residue is compared with a first result residue of the second operation circuitry. The extended result residue less both the first partial result residue and a second portion residue of the extended result received from the residue check path as a second partial result residue is compared with a second result residue of the second operation circuitry.

The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.

An information handling system includes a non-volatile dual in-line memory module (NVDIMM) and a processor. The NVDIMM instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated on the information handling system. The second partition is accessible to the operating system. The first partition includes a first region and a second region. The processor boots the information handling system to configure the NVDIMM based upon information from the first region, detects an error associated with the NVDIMM, and writes information associated with the error to the second region.

A method includes generating an extended result from a first operation circuitry having a result register bit width greater than a bus width associated with a residue check path of a second operation circuitry associated with a floating point unit. An extended result residue less a first portion residue of the extended result received from the residue check path is stored as a first partial result residue. The first partial result residue is compared with a first result residue of the second operation circuitry. The extended result residue less both the first partial result residue and a second portion residue of the extended result received from the residue check path as a second partial result residue is compared with a second result residue of the second operation circuitry.

An information handling system includes a non-volatile dual in-line memory module (NVDIMM) and a processor. The NVDIMM instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system instantiated on the information handling system. The second partition is accessible to the operating system. The first partition includes a first region and a second region. The processor boots the information handling system to configure the NVDIMM based upon information from the first region, detects an error associated with the NVDIMM, and writes information associated with the error to the second region.

A method of ensuring operation of a calculator includes causing, by a CPU, the calculator to perform a predetermined operation verification calculation of which a correct value that is a resultant value in normal operation is set to ae predetermined value; acquiring, by the CPU, the resultant value of the calculation; referencing, by the CPU using a relative address referencing capability of the CPU, an address that is stored in an address acquired by adding the acquired resultant value to the starting address of the memory; and executing, by the CPU, a function stored at the referenced address.