A method of verifying processing logic of a graphics processing unit receives a test task including a predefined set of instructions for execution on the graphics processing unit, the predefined set of instructions being configured to perform a predetermined set of operations on the graphics processing unit when executed for predefined input data. In a test phase, the test task is processed by executing the predefined set of instructions for the predefined input data first and second times at the graphics processing unit so as to, respectively, generate first and second outputs. A fault signal is raised if the first and second outputs do not match.

According to certain embodiments, a system includes one or more processors and one or more computer-readable non-transitory storage media comprising instructions that, when executed by the one or more processors, cause one or more components to perform operations including executing a software process of a secondary instance, the secondary instance running in parallel with a primary instance and associated with a plurality of cores including a bootstrap core, registering a non-maskable interrupt for the bootstrap core in the secondary instance, determining whether the secondary instance is in a fault state, wherein, if the secondary instance is in the fault state, halting the plurality of cores associated with the secondary instance, without impact to the primary instance, and recovering the bootstrap core by switching a context of the bootstrap core from the secondary instance to the primary instance via the non-maskable interrupt.

The application provides a method and an apparatus for testing an autonomous vehicle, and a storage medium, where the method includes: obtaining detection information of the autonomous vehicle, where the detection information is configured to indicate the test result obtained when the detecting apparatus in the autonomous vehicle tests the autonomous vehicle; further, generating a test interface according to the obtained detection information, and displaying the test interface, so that the tester can visually check various test information of the autonomous vehicle during the road running test, thereby not only saving a labor cost, but also improving a test efficiency of the road running test.

Systems, methods, and apparatuses for autonomous functional testing of a processor are described. In one example, a processor includes a plurality of processor cores that are each coupled to a respective power management agent circuit; a cache shared by the plurality of processor cores; and a control register, that when set, causes: a save of a state of a first processor core of the plurality of processor cores to storage, a transfer of control of the first processor core to a power management agent circuit of the first processor core, isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, performance of one or more functional tests from the cache on the first processor core caused by the power management agent circuit to generate a test result, removal of the isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, and a transfer of the control by the power management agent circuit back to the first processor core.

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

Various embodiments include components (e.g., a processor in a vehicle advanced driver assistance system) configured to identify subsystems that require testing in order to verify their compliance with a safety requirement. The components may determine whether verification of compliance requires that the subsystems be tested at PON, at POFF, during runtime or a combination thereof, dynamically determine the achievable parallelism for testing the identified subsystems, dynamically determine coverage level requirements for performing or executing built in self tests (BISTs) on each identified subsystem, and perform or execute the BISTs on the subsystems at the determined level of parallel and at the determined coverage level.

According to certain embodiments, a system includes one or more processors and one or more computer-readable non-transitory storage media comprising instructions that, when executed by the one or more processors, cause one or more components to perform operations including executing a software process of a secondary instance, the secondary instance running in parallel with a primary instance and associated with a plurality of cores including a bootstrap core, registering a non-maskable interrupt for the bootstrap core in the secondary instance, determining whether the secondary instance is in a fault state, wherein, if the secondary instance is in the fault state, halting the plurality of cores associated with the secondary instance, without impact to the primary instance, and recovering the bootstrap core by switching a context of the bootstrap core from the secondary instance to the primary instance via the non-maskable interrupt.

Methods and computing devices for allocating test pods to a distributed computing system for executing a test plan on a device-under-test (DUT). Each test pod may include a test microservice including one or more test steps and an event microservice specifying function relations between the test microservice and other test microservices. The test pods are allocated to different servers to perform a distributed execution of the test plan on the DUT through one or more test interfaces.

A CPU having a plurality of cores is configured by determining a number of cores required for operation of the CPU. Each respective core is tested, and a performance parameter of the respective core is determined based on the test. The respective core is then classified for suitability to perform a set of functions based on the performance parameter of the respective core. If at least the number of cores required for operation of the CPU are classified for suitability to perform the set of functions, a subset of suitable cores is defined, the subset including cores that are classified for the set of functions and at least the number of cores required for operation of the CPU. The required number of cores from among the subset of cores are then enabled.

Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.