A semiconductor device includes a data bus, a data memory, a selector, a processor, and a debug controller. The selector is configured to be controlled by the debug controller to be in either a first selecting state in which the processor transmits a first signal to the data bus and a second selecting state in which the debug controller transmits a second signal to the data bus. The debug controller is configured to control the state of the selector based on the reception state of a predetermined command from an external device as well as the states of a read enable signal and a write enable signal from the processor such that, when the selector is in the second selecting state, the debug controller accesses the data bus via the selector.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

A compliance testing system for generating a compliance prediction for a test target. Determinate factors and indeterminate factors associated with a current testing stage of the test target are identified. A test vector for each of the indeterminate factors is generated. A set of matching test vectors for each of the indeterminate factors is determined based on the test vector. The set of matching test vectors are determined using data extracted from at least one profile model. A cumulative factor value is determined for each of the indeterminate factors based on the set of matching test vectors. A first outcome is generated for each of the determinate factors. A second outcome is generated for each of the indeterminate factors, based on the cumulative factor value and the set of matching test vectors. A compliance prediction is generated for the test target based on the first outcome and the second outcome.

Techniques are disclosed relating to cache debug using control registers based on debug commands. In some embodiments, an apparatus includes a processor core, debug circuitry, and control circuitry. In some embodiments, the debug circuitry is configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs. In some embodiments, the control circuitry is configured to, in response to an abstract command to read data from the cache: write cache address information to a first control register, assert a trigger signal to cause a read of the data from the cache to a second control register, based on the cache address information in the first control register, and send data from the second control register to the debug circuitry. In various embodiments, this may facilitate hardware cache debug using debug circuitry that also controls software debugging.

An automated test equipment (ATE) system comprises a system controller communicatively coupled to a tester processor, where the system controller is operable to transmit instructions to the tester processor, and where the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The apparatus also comprises an FPGA programmed to support a first protocol communicatively coupled to the tester processor comprising at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing a DUT of the plurality of DUTs. Further, the apparatus comprises a bus adapter comprising a protocol converter module operable to convert signals associated with the first protocol received from the FPGA to signals associated with a second protocol prior to transmitting the signals to the DUT, wherein the DUT communicates using the second protocol.

A test controller interfacing between a master computing device and slave computing devices includes a processor configured to launch a master application on the master computing device and a slave application to be tested on each respective slave computing device, with each slave application being the same as the master application. The processor is also configured to receive from the master computing device an input test command along with a test result based on execution of the input test command by the master application, and transmit the received input test command to each slave computing device. In addition, the processor is configured to receive a respective test result from each slave computing device based on execution of the received input test command, and compare each respective test result from the slave computing devices to the test result from the master computing device.

A memory device includes a load generator and a memory controller. The load generator outputs loads for first accesses directed to a memory, irrespective of attributes and characteristics of master devices. The load generator outputs the loads at a constant bandwidth without a change in a bandwidth for outputting the loads. The memory controller receives the loads from the load generator, or receives requests for second accesses directed to the memory from the master devices through a bus. The memory controllers processes the loads such that operations associated with the first accesses are performed in the memory, or processes the requests such that operations associated with the second accesses are performed in the memory. The memory controller processes the loads in a manner which is identical to a manner of processing the requests.

An automated key pressing device includes a loading stage, a base, a transmission module, two key pressing modules. The base is located at one side of the loading stage. The transmission module is reciprocatedly slidable on the base. One of the key pressing modules is disposed on the transmission module, and extends outwardly towards the loading stage for pressing one key of a keyboard by the transmission module. The other key pressing module is located on the base and extends outwardly towards the loading stage for pressing another key of the keyboard. The one of the key pressing modules is more prominently extended outwardly than the other. The control unit electrically connected to the key pressing modules and the transmission module.

An automated key pressing device includes a loading stage, a base, a transmission module, two key pressing modules. The base is located at one side of the loading stage. The transmission module is reciprocatedly slidable on the base. One of the key pressing modules is disposed on the transmission module, and extends outwardly towards the loading stage for pressing one key of a keyboard by the transmission module. The other key pressing module is located on the base and extends outwardly towards the loading stage for pressing another key of the keyboard. The one of the key pressing modules is more prominently extended outwardly than the other. The control unit electrically connected to the key pressing modules and the transmission module.

The invention refers to a method for accessing an passenger transportation device control means comprising several separated printed circuit boards (PCB), whereby each of these PCBs comprises a unique identifier (ID), and in which method the passenger transportation device control means comprise a matching table which is used by the passenger transportation device control means to perform a matching test to check the identifier of at least two of the PCBs and to put the passenger transportation device control means into normal operation only if their IDs match the IDs of the matching table. A service technician connects via a key to the passenger transportation device control means, which key enables the service technician to set the passenger transportation device control means into a fault finding mode, in which fault finding mode the passenger transportation device control means are initiated to skip the matching test before getting into operation, whereby the fault finding mode is terminated at the latest when the service technician terminates the key-based connection with the passenger transportation device control means.