An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes a first processor configured to execute a custom BMC firmware stack, and a second processor including executable instructions for receiving a request to perform a test on the first processor in which the request is received through a secure communication session established with a remote IHS. The instructions further perform the acts of controlling the first processor to perform the test according to the request, the first processor generating test results associated with the test, and transmitting the test results to the remote IHS through the secure communication session.

Systems, methods, and apparatuses for autonomous functional testing of a processor are described. In one example, a processor includes a plurality of processor cores that are each coupled to a respective power management agent circuit; a cache shared by the plurality of processor cores; and a control register, that when set, causes: a save of a state of a first processor core of the plurality of processor cores to storage, a transfer of control of the first processor core to a power management agent circuit of the first processor core, isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, performance of one or more functional tests from the cache on the first processor core caused by the power management agent circuit to generate a test result, removal of the isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, and a transfer of the control by the power management agent circuit back to the first processor core.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.

A semiconductor device includes a data bus, a data memory, a selector, a processor, and a debug controller. The selector is configured to be controlled by the debug controller to be in either a first selecting state in which the processor transmits a first signal to the data bus and a second selecting state in which the debug controller transmits a second signal to the data bus. The debug controller is configured to control the state of the selector based on the reception state of a predetermined command from an external device as well as the states of a read enable signal and a write enable signal from the processor such that, when the selector is in the second selecting state, the debug controller accesses the data bus via the selector.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

A configuration generating method for devices is applied to connecting ports and external devices connected to the connecting ports. The method includes the following steps: determining communication protocol types of the connecting ports respectively; generating a sequence list according to a plurality of device data, wherein each of the device data is corresponding to a communication protocol, the device data with ccTalk protocol are categorized in a first priority group, the device data with MDB protocol are categorized in a third sequence group, the device data other than those of the first priority group and the third priority group are categorized in a second priority group; and, testing the external devices sequentially and generating communication results according to the sequence list and the device data corresponding to the communication protocol types, and then generating a connecting ports configuration data of connecting ports according to the communication results.

One or more embodiments provide a heterogeneous test equipment interfacing apparatus. The heterogeneous test equipment interfacing apparatus includes a plurality of data intermediate apparatuses connected to a plurality of environment test chambers; and at least one computer apparatus interoperating with the plurality of data intermediate apparatuses. Each of the plurality of data intermediate apparatuses is configured to convert an electric signal received from at least one environment test chamber interoperating with a corresponding data intermediate apparatus from among the plurality of environment test chambers into a data signal based on an SNMP protocol, output the data signal and, output a control signal for controlling the at least one environment test chamber interoperating with a corresponding data intermediate apparatus according to an operation control instruction received from the at least one computer apparatus.

A configuration generating method for devices is applied to connecting ports and external devices connected to the connecting ports. The method includes the following steps: determining communication protocol types of the connecting ports respectively; generating a sequence list according to a plurality of device data, wherein each of the device data is corresponding to a communication protocol, the device data with ccTalk protocol are categorized in a first priority group, the device data with MDB protocol are categorized in a third sequence group, the device data other than those of the first priority group and the third priority group are categorized in a second priority group; and, testing the external devices sequentially and generating communication results according to the sequence list and the device data corresponding to the communication protocol types, and then generating a connecting ports configuration data of connecting ports according to the communication results.

A compliance testing system for generating a compliance prediction for a test target. Determinate factors and indeterminate factors associated with a current testing stage of the test target are identified. A test vector for each of the indeterminate factors is generated. A set of matching test vectors for each of the indeterminate factors is determined based on the test vector. The set of matching test vectors are determined using data extracted from at least one profile model. A cumulative factor value is determined for each of the indeterminate factors based on the set of matching test vectors. A first outcome is generated for each of the determinate factors. A second outcome is generated for each of the indeterminate factors, based on the cumulative factor value and the set of matching test vectors. A compliance prediction is generated for the test target based on the first outcome and the second outcome.