An automated fault injection testing and analysis approach drives fault injection into a processor driven instruction sequence to quantify and define susceptibility to external fault injections for manipulating instruction execution and control flow of a set of computer instructions. A fault injection such as a voltage or electromagnetic pulse directed at predetermined locations on a processor (Central Processing Unit, or CPU) alters a result of a processor instruction to change values or execution paths. One or more quantified injections define an injection chain that causes a predictable or repeatable deviant result from an expected execution path through the code executed by the processor. Based on accumulation of fault injections and results, a repeatable injection chain and probability identifies an external action taken on a processing device to cause unexpected results that differ from an expected execution of a program or set of computer instructions.

An automated fault injection testing and analysis approach drives fault injection into a processor driven instruction sequence to quantify and define susceptibility to external fault injections for manipulating instruction execution and control flow of a set of computer instructions. A fault injection such as a voltage or electromagnetic pulse directed at predetermined locations on a processor (Central Processing Unit, or CPU) alters a result of a processor instruction to change values or execution paths. One or more quantified injections define an injection chain that causes a predictable or repeatable deviant result from an expected execution path through the code executed by the processor. Based on accumulation of fault injections and results, a repeatable injection chain and probability identifies an external action taken on a processing device to cause unexpected results that differ from an expected execution of a program or set of computer instructions.

A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.

Techniques for automatically selecting device tests for testing devices configured for operation in wireless communication networks, based upon maintenance releases (MRs) received from original equipment manufacturers. When an MR with changes for a device is received, the MR may be analyzed in order to determine what the changes pertain to with respect to the device. The changes may be clustered with respect to requirements for the changes and a knowledge base may be consulted by a recommendation engine in order to determine candidate tests for testing the MR. The candidate tests may be based upon previous tests, failed tests and, relevant tests. Based at least in part on the identified previous tests, failed tests and relevant tests, one or more tests may be selected for testing devices with respect to the newly received MR.

Techniques for automatically selecting device tests for testing devices configured for operation in wireless communication networks, based upon maintenance releases (MRs) received from original equipment manufacturers. When an MR with changes for a device is received, the MR may be analyzed in order to determine what the changes pertain to with respect to the device. The changes may be clustered with respect to requirements for the changes and a knowledge base may be consulted by a recommendation engine in order to determine candidate tests for testing the MR. The candidate tests may be based upon previous tests, failed tests and, relevant tests. Based at least in part on the identified previous tests, failed tests and relevant tests, one or more tests may be selected for testing devices with respect to the newly received MR.

Examples of electronic devices are described herein. In some examples, an electronic device may include a communication interface to receive information from a peripheral device. In some examples, the electronic device may include logic circuitry to determine a target latency tolerance reporting (LTR) value based on the information via a machine learning model.

Examples of electronic devices are described herein. In some examples, an electronic device may include a communication interface to receive information from a peripheral device. In some examples, the electronic device may include logic circuitry to determine a target latency tolerance reporting (LTR) value based on the information via a machine learning model.

In an approach to inspecting integrated circuits, a system includes a first detection system and a second detection system for measuring electroluminescent (EL) images from a device under test (DUT); and a controller. The controller is configured to: measure EL emissions from the DUT with the first and the second detection systems to obtain a first and a second EL test data; compare the first and the second EL test data to a reference model of a reference device, the reference model developed based on measured EL reference data, synthetic EL reference data, or a combination thereof obtained from the reference device or a reference design of the reference device; and determine whether the DUT is in accordance with the reference device, based at least in part on the comparison of the first and the second EL test data to the reference model of the reference device.

There is presented a system and method for detecting mobile device fault conditions, including detecting fault conditions by software operating on the mobile device. In one embodiment, the present invention provides for systems and methods for detecting a that a mobile device has a cracked screen, and reporting the status of the screen, working or not, so that appropriate action may be taken by a third party. In one embodiment, the data obtained by testing of the mobile device is encrypted to prevent tampering or spoofing by the user of the mobile device, and is suitably decrypted by the recipient or software running within a server.

The present invention relates to a method of validating a memory device. The method includes validating a second memory device based on one or more first microcode instructions stored in a validated predetermined part of a first memory device to detect the operational status of the second memory device. Further, the method includes receiving one or more second microcode instructions upon validating the second memory device. Finally, validating the first memory device based on the one or more second microcode instructions stored in the second memory device to detect the operational status of the first memory device.