Various embodiments are provided herein for checking proper inclusion and sequencing of drug modules in a combinatorial drug delivery device.

In one embodiment, one or more control units may store a position tracker associated with a first window of memory blocks and allow a first processing unit to write data within the first window. The control units may receive, from a second processing unit, a request for reading data with a memory-reading address, compare the memory-reading address to a first starting address of the first window, and prevent the second processing unit from reading the data when the memory-reading address is greater than or equal to the first starting address of the first window. The control units may store, when the data writing process is complete, an updated position tracker of a second window of memory blocks and allow the second processing unit to read the data based on a determination that the memory-reading address is less than a second starting address of the second window.

Examples described herein include systems and methods which include an apparatus comprising a memory array including a plurality of memory cells and a memory controller coupled to the memory array. The memory controller comprises a memory mapper configured to configure a memory map on the basis of a memory command associated with a memory access operation. The memory map comprises a specific sequence of memory access instructions to access at least one memory cell of the memory array. For example, the specific sequence of memory access instructions for a diagonal memory command comprises a sequence of memory access instructions that each access a memory cell along a diagonal of the memory array.

In one embodiment, one or more control units may store a position tracker associated with a first window of memory blocks and allow a first processing unit to write data within the first window. The control units may receive, from a second processing unit, a request for reading data with a memory-reading address, compare the memory-reading address to a first starting address of the first window, and prevent the second processing unit from reading the data when the memory-reading address is greater than or equal to the first starting address of the first window. The control units may store, when the data writing process is complete, an updated position tracker of a second window of memory blocks and allow the second processing unit to read the data based on a determination that the memory-reading address is less than a second starting address of the second window.

A system includes a conditioning circuit, resistors connected to pins of the conditioning circuit, and measurement sensors connected to pins of the conditioning circuit. The conditioning circuit is configured to determine resistance values of the resistors and to determine a set of addresses for the measurement sensors based upon a combination of the resistance values of the resistors.

A method of broadcasting event messages in a system-on-chip having system circuitry and monitoring circuitry for monitoring the system circuitry, the monitoring circuitry comprising units connected in a tree-based structure for routing communications through the system-on-chip, the tree-based structure comprising branches extending from a root unit, each branch comprising a plurality of units, each unit connected to a single unit above in the branch and a single unit below in the branch, whereby each unit routes communications to and from individually addressable entities above that unit in its branch, the tree-based structure further comprising crosslinks connecting corresponding units of adjacent branches, the method comprising: if an event is generated at an event unit or its local subsystem, routing an event message directly from that event unit to: any adjacent unit above the event unit in the event unit's branch, any adjacent unit below the event unit in the event unit's branch, and any corresponding unit of an adjacent branch to which the event unit is connected via a crosslink.

A system of electronic modules is described, along with a method of assigning addresses to the modules. The modules are communicatively connected along a communication path, and are also communicatively connected to an address bus. Adders are positioned along the address bus, with at least one adder located between each pair of modules. When any module is assigned an address, its adjacent adder will increment the address and assign the incremented address to the next-adjacent module.

A method of reconfiguring an addressing mechanism in a system-on-chip comprising system circuitry and monitoring circuitry having tree-structured units for routing communications through the system, includes sending a discovery message, receiving discovery responses from the units, each discovery response identifying the number of individually addressable entities in that unit and those units in the branch above that unit; in response to not receiving a response from one or more units, determining that one of those units is defective; enabling a crosslink between a first unit in the same branch as the defective unit and a second unit in an adjacent branch; sending a further discovery message; receiving a further discovery response from the second unit identifying the number of individually addressable entities in that second unit, those units in the branch above that second unit, the first unit, and those units in the branch above the first unit; and reconfiguring the address of the crosslink so as to cause a subsequent communication to an individually addressable entity in the defective unit's branch to be routed via the adjacent branch and the crosslink, thereby bypassing the defective unit.

A system of electronic modules is described, along with a method of assigning addresses to the modules. The modules are communicatively connected along a communication path, and are also communicatively connected to an address bus. Adders are positioned along the address bus, with at least one adder located between each pair of modules. When any module is assigned an address, its adjacent adder will increment the address and assign the incremented address to the next-adjacent module.

A memory chip is described. The memory chip includes self identification circuitry to self identify the memory chip. The self identification circuitry is to determine a resistance of a resistor and correlate the memory chip's identity to the resistance. A registering clock driver (RCD) chip is described. The RCD chip includes a controller. The controller is to receive provisional IDs (PIDs) from memory chips on a same memory module as the RCD chip. The controller is to program the memory chips with respective logical IDs (LIDs) based on a correlation of the PIDs and the LIDs.