A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

Entries in a cluster-to-caching agent map table of a data processing network identify one or more caching agents in a caching agent cluster. A snoop filter cache stores coherency information that includes coherency status information and a presence vector, where a bit position in the presence vector is associated with a caching agent cluster in the cluster-to-caching agent map table. In response to a data request, a presence vector in the snoop filter cache is accessed to identify a caching agent cluster and the map table is accessed to identify target caching agents for snoop messages. In order to reduce message traffic, snoop message are sent only to the identified targets.

A method and system for efficiently executing a delegate of a program by a processor coupled to an external memory. A payload including state data or command data is bound with a program delegate. The payload is mapped with the delegate via the payload identifier. The payload is pushed to a repository buffer in the external memory. The payload is flushed by reading the payload identifier and loading the payload from the repository buffer. The delegate is executed using the loaded payload.

The disclosure relates to technology for bulk initialization of memory in a computer system. The computer system comprises a processor core comprising a load store unit and a last level cache in communication with the processor core. The last level cache is configured to receive bulk store operations from the load store unit. Each bulk store operation includes a physical address in the memory to be initialized. The last level cache is configured to send multiple write transactions to the memory for each bulk store operation to perform a bulk initialization of the memory for each bulk store operation. The last level cache is configured to track status of the bulk store operations.

Apparatuses, systems, and techniques to select cache policies. In at least one embodiment, a system causes one or more cache policies of one or more caches to be selected based, at least in part, on one or more neural networks to use data stored in the one or more caches.

Aspects of the present disclosure relate to data cache management. In embodiments, a logical block address (LBA) bucket is established with at least one logical LBA group. Additionally, at least one LBA group is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array. Further, the association includes binding the two or more distinctly sized cache slots with at least one LBA group and mapping the bound distinctly sized cache slots in a searchable data structure. Furthermore, the searchable data structure identifies relationships between slot pointers and key metadata.

A fleet of query accelerator nodes is established for a data store. Each accelerator node caches data items of the data store locally. In response to determining that an eviction criterion has been met, one accelerator node removes a particular data item from its local cache without notifying any other accelerator node. After the particular data item has been removed, a second accelerator node receives a read query for the particular data item and provides a response using a locally-cached replica of the data item.

A computer-implemented method for synchronizing local caches is disclosed. The method may include receiving a content update which is an update to a data entry stored in local caches of each of a plurality of remote servers. The method may include transmitting the content update to a first remote server to update a corresponding data entry in a local cache of the first remote server. Further, the method may include generating an invalidation command, indicating the change in the corresponding data entry. The method may include transmitting the invalidation command from the first remote server to the message server. The method may include generating, by the message server, a plurality of partitions based on the received invalidation command. The method may include transmitting, from the message server to each of the remote servers, the plurality of partitions, so that the remote servers update their respective local caches.

Embodiments of the present disclosure relate to a system and an operating method of the system. Based on some embodiments of the disclosed technology, the system may include a random access memory structured to include memory cells to store data, a cache memory configured to cache at least part of the data, and a processor in communication with the random access memory and the cache memory to access at least part of the data from the random access memory or cache memory. The system may determine a cache hit ratio for the cache memory, and may set an operating frequency of the random access memory based on the cache hit ratio.

An electronic device includes one or more processors and a cache that stores data entries. The electronic device transmits a request for translation of a first address to the cache. In accordance with a determination that the request is not satisfied by the data entries in the cache, the electronic device transmits the request to memory that is distinct from the cache, and receives data including a second address corresponding to the first address. In accordance with a determination that the data does not satisfy cache promotion criteria, the electronic device replaces an entry at a first priority level in the cache with the data. In accordance with a determination that the data satisfies the cache promotion criteria, the electronic device replaces an entry at a second priority level that is a higher priority level than the first priority level in the cache with the data including the second address.