Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric; a first root port and a second root port, each of the first and second root ports coupled to a corresponding IOMMU of the first and second IOMMUs; and a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports, wherein each of the first and second root ports comprises hardware control logic operative to: synchronize the first and second root ports.

A method may include accessing, by a first apparatus, a queue, wherein the queue may be accessible by a second apparatus, and the first apparatus may be connected to the second apparatus by a coherent interface, and indicating, by the coherent interface, to the second apparatus, the accessing. The indicating may include indicating by a monitoring mechanism. The indicating may include generating a monitoring request. The indicating may include generating, based on the monitoring request, an alert. The queue may include a submission queue. The queue may include a completion queue. The accessing may include reading an entry from the queue. The accessing may include writing an entry to the queue. The entry may include a command. The entry may include a completion. The first apparatus may include a host, and the second apparatus may include a device. The queue may be located at the host.

A memory module includes a device memory configured to store data and including a first memory area and a second memory area, and a controller including an accelerator circuit. The controller is configured to control the device memory, transmit a command to exclude the first memory area from the system memory map to a host processor in response to a mode change request, and modify a memory configuration register to exclude the first memory area from the memory configuration register. The accelerator circuit is configured to use the first memory area to perform an acceleration operation.

A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.

A data processing method is applied to a digital interface, which includes: reading data cached by a data source, where the data source includes a video source and an auxiliary data source; outputting video data, if the video data cached by the video source is not empty, where when the video data is output, corresponding position marks are at start and end positions of a frame structure of the video data and at start and end positions of a row structure of the video data; and outputting auxiliary data, if the video data cached by the video source is empty, the auxiliary data cached by the auxiliary data source is not empty and the frame structure or the row structure of the video data has been output, where when the auxiliary data is output, corresponding position marks are at a start position and an end position of the auxiliary data.

A system includes a memory including a plurality of rings, an endpoint associated with a ring of the plurality of rings, and a gateway. The gateway is configured to receive a notification from the endpoint regarding a packet made available in the ring associated with the endpoint, access the ring with an RDMA read request, retrieve the packet made available in the ring, and forward the packet on an external network.

A gateway for interfacing a host with a subsystem for acting as a work accelerator to the host. The gateway enables the transfer of batches of data to the subsystem at precompiled data exchange synchronisation points. The gateway acts to route data between accelerators which are connected in a scaled system of multiple gateways and accelerators using a global address space set up at compile time of an application to run on the computer system.

Examples herein describe an accelerator device that shares the same coherent domain as hardware elements in a host computing device. The embodiments herein describe a mix of hardware and software coherency which reduces the overhead of managing data when large chunks of data are moved from the host into the accelerator device. In one embodiment, an accelerator application executing on the host identifies a data set it wishes to transfer to the accelerator device to be processed. The accelerator application transfers ownership from a home agent in the host to the accelerator device. A slave agent can then take ownership of the data. As a result, any memory operation requests received from a requesting agent in the accelerator device can gain access to the data set in local memory via the slave agent without the slave agent obtaining permission from the home agent in the host.

Disclosed embodiments relate to a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.

Disclosed embodiments relate to a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.