Aspects of the disclosure are directed to hardware interconnects and corresponding devices and systems for non-coherently accessing data in shared memory devices. Data produced and consumed by devices implementing the hardware interconnect can read and write directly to a memory device shared by multiple devices, and limit coherent memory transactions to relatively smaller flags and descriptors used to facilitate data transmission as described herein. Devices can communicate less data on input/output channels, and more data on memory and cache channels that are more efficient for data transmission. Aspects of the disclosure are directed to devices configured to process data that is read from the shared memory device. Devices, such as hardware accelerators, can receive data indicating addresses for different data buffers with data for processing, and non-coherently read or write the contents of the data buffers on a memory device shared between the accelerators and a host device.

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can include trigger instructions defined in metadata for a particular memory object. Each trigger instruction can comprise a single instruction and action based on reference to a specific object to initiate or perform defined actions such as pre-fetching other objects or executing a trigger program.

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can include trigger instructions defined in metadata for a particular memory object. Each trigger instruction can comprise a single instruction and action based on reference to a specific object to initiate or perform defined actions such as pre-fetching other objects or executing a trigger program.

A method for execution by a dispersed storage network (DSN) managing unit includes receiving access information from a plurality of distributed storage and task (DST) processing units via a network. Cache memory utilization data is generated based on the access information. Configuration instructions are generated for transmission via the network to the plurality of DST processing units based on the cache memory utilization data.

A method for execution by a dispersed storage network (DSN) managing unit includes receiving access information from a plurality of distributed storage and task (DST) processing units via a network. Cache memory utilization data is generated based on the access information. Configuration instructions are generated for transmission via the network to the plurality of DST processing units based on the cache memory utilization data.

In exemplary aspects of cache coherency management, a first request is received and includes an address of a first memory block in a shared memory. The shared memory includes memory blocks of memory devices associated with respective processors. Each of the memory blocks are associated with one of a plurality of memory categories indicating a protocol for managing cache coherency for the respective memory block. A memory category associated with the first memory block is determined and a response to the first request is based on the memory category of the first memory block. The first memory block and a second memory block are included in one of the same memory devices, and the memory category of the first memory block is different than the memory category of the second memory block.

The disclosure relates to technology for bulk initialization of memory in a computer system. The computer system comprises a processor core comprising a load store unit and a last level cache in communication with the processor core. The last level cache is configured to receive bulk store operations from the load store unit. Each bulk store operation includes a physical address in the memory to be initialized. The last level cache is configured to send multiple write transactions to the memory for each bulk store operation to perform a bulk initialization of the memory for each bulk store operation. The last level cache is configured to track status of the bulk store operations.

A computer-implemented method for managing cache utilization of at least a first processor when sharing a cache with a further processor. The method includes: executing, during a first regulation interval, a first application on a first processor, wherein the first application causes at least one block to be mapped from an external memory to a shared cache according to a cache utilization policy associated with the first application; monitoring a utilization of the shared cache by the first processor during the first regulation interval; comparing the utilization of the shared cache by the first processor to a cache utilization condition associated with the first processor; and adjusting the cache utilization policy associated with the first application, when the utilization of the shared cache by the first processor exceeds the cache utilization condition associated with the first processor.

A computer-implemented method for managing cache utilization of at least a first processor when sharing a cache with a further processor. The method includes: executing, during a first regulation interval, a first application on a first processor, wherein the first application causes at least one block to be mapped from an external memory to a shared cache according to a cache utilization policy associated with the first application; monitoring a utilization of the shared cache by the first processor during the first regulation interval; comparing the utilization of the shared cache by the first processor to a cache utilization condition associated with the first processor; and adjusting the cache utilization policy associated with the first application, when the utilization of the shared cache by the first processor exceeds the cache utilization condition associated with the first processor.

Techniques are disclosed relating to filtering messages. A computer system may detect an occurrence of an event of a particular type. The computer system may determine whether to enqueue, in a message queue, a message that identifies a set of tasks to be performed in relation to the event. The determination may be based on a response received from a cache that stores a subset of filter rules of a filter rules table. Based on the response indicating a cache miss, the computer system may enqueue the message in the message queue. A process that processes the message may be operable to resolve the cache miss by 1) accessing a filter rule from the filter rules table that indicates whether messages for events of the particular type should be enqueued in the message queue and 2) updating the cache to store the filter rule.