According to one embodiment, a memory system includes a non-volatile memory array with a plurality of memory cells. Each memory cell is a multilevel cell to which multibit data can be written. The non-volatile memory array includes a first storage region in which the multibit data of a first bit level is written and a second storage region in which data of a second bit level less than the first bit level is written. A memory controller is configured to move pieces of data from the first storage region to the second storage region based on the number of data read requests for the pieces of data received over a period of time or on external information received from a host device that sends read requests.

According to one embodiment, a memory system includes a non-volatile memory array with a plurality of memory cells. Each memory cell is a multilevel cell to which multibit data can be written. The non-volatile memory array includes a first storage region in which the multibit data of a first bit level is written and a second storage region in which data of a second bit level less than the first bit level is written. A memory controller is configured to move pieces of data from the first storage region to the second storage region based on the number of data read requests for the pieces of data received over a period of time or on external information received from a host device that sends read requests.

A method for execution by a dispersed storage network (DSN) managing unit includes receiving access information from a plurality of distributed storage and task (DST) processing units via a network. Cache memory utilization data is generated based on the access information. Configuration instructions are generated for transmission via the network to the plurality of DST processing units based on the cache memory utilization data.

A method for execution by a dispersed storage network (DSN) managing unit includes receiving access information from a plurality of distributed storage and task (DST) processing units via a network. Cache memory utilization data is generated based on the access information. Configuration instructions are generated for transmission via the network to the plurality of DST processing units based on the cache memory utilization data.

Provided are a computer program product, system, and method for adjusting active cache size based on cache usage. An active cache in at least one memory device caches tracks in a storage during computer system operations. An inactive cache in the at least one memory device is not available to cache tracks in the storage during the computer system operations. During caching operations in the active cache, information is gathered on cache hits to the active cache and cache hits that would occur if the inactive cache was available to cache data during the computer system operations. The gathered information is used to determine whether to configure a portion of the inactive cache as part of the active cache for use during the computer system operations.

Provided are a computer program product, system, and method for adjusting active cache size based on cache usage. An active cache in at least one memory device caches tracks in a storage during computer system operations. An inactive cache in the at least one memory device is not available to cache tracks in the storage during the computer system operations. During caching operations in the active cache, information is gathered on cache hits to the active cache and cache hits that would occur if the inactive cache was available to cache data during the computer system operations. The gathered information is used to determine whether to configure a portion of the inactive cache as part of the active cache for use during the computer system operations.

A data management method causes a computer to execute processing including: creating, when a predetermined data processing program performs data processing, based on an access frequency to a data store, high-frequency state item list information obtained by listing high-frequency state items of which the access frequency is high; determining, when state information that includes a value of the high-frequency state item is written to the data store, whether or not the state information corresponds to the high-frequency state item with reference to the high-frequency state item list information; grouping and writing pieces of the state information of a plurality of the high-frequency state item.

A method performed by a processor to improve wear-leveling in a cross-point (X3D) memory, comprises detecting, by a processor coupled to the X3D memory, a trigger event, wherein the X3D memory comprises a first section of memory units and a second section of memory units, and in response to detecting the trigger event, relocating, by the processor, data stored in a first memory unit of the first section of memory units to a memory unit adjacent to a last memory unit of the first section of memory units, and relocating, by the processor, data stored in a first memory unit of the second section of memory units to a memory unit adjacent to a last memory unit of the second section of memory units.

A method performed by a processor to improve wear-leveling in a cross-point (X3D) memory, comprises detecting, by a processor coupled to the X3D memory, a trigger event, wherein the X3D memory comprises a first section of memory units and a second section of memory units, and in response to detecting the trigger event, relocating, by the processor, data stored in a first memory unit of the first section of memory units to a memory unit adjacent to a last memory unit of the first section of memory units, and relocating, by the processor, data stored in a first memory unit of the second section of memory units to a memory unit adjacent to a last memory unit of the second section of memory units.

Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.