Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

Apparatuses and methods can be related to encoding traffic between a host and a DLA. Traffic between a host can be encoded utilizing an autoencoder. Encoding traffic between a host and a DLA changes the bandwidth of the traffic. Changing the bandwidth of the traffic prevents the correlation between the bandwidth and the input from which the traffic is generated.

Some embodiments provide a program that receives a first set of data and a first greenhouse gas emission value. The program stores, in a cache, the first set of data and the first greenhouse gas emission value. The program receives a second set of data and a second greenhouse gas emission value. The program stores, in the cache, the second set of data and the second greenhouse gas emission value. The program receives a third set of data and a third greenhouse gas emission value. The program determines one of the first and second sets of data to remove from the cache based on the first and second greenhouse gas emission values. The program replaces, in the cache, one of the first and second sets of data and the corresponding first or second greenhouse gas emission value with the third set of data and the third greenhouse gas emission value.

Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

In a data processing system that comprises a memory 8 comprising N memory banks 11, a memory controller is configured to store one or more N data unit×N data unit arrays of data in the memory 8 such that each data unit in each row of each N×N data unit array is stored in a different memory bank of the N memory banks 11, and such that each data unit in each column of each N×N data unit array is stored in a different memory bank of the N memory banks 11.

A host device includes a unit processor configured to generate a near data processing (NDP) request, a host expansion control circuit configured to receive the NDP request; and a local memory device configured to store data corresponding to the NDP request according to control by the expansion control circuit. In response to receiving the NDP request, the host expansion control circuit performs a request processing operation to perform a read or a write operation corresponding to the NDP request on the local memory device and performs a computation operation using the requested data corresponding to the NDP request.

Cache-based trace logging using tags in system memory. A processor influxes a cache line into a first cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in system memory and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line has been previously captured by a trace has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

A cache management circuit that includes a predictive adjustment circuit configured to predictively generate cache control information based on a cache hit-miss indicator and the retention ranks of accessed cache lines to improve cache efficiency is disclosed. The predictive adjustment circuit stores the cache control information persistently, independent of whether the data remains in cache memory. The stored cache control information is indicative of prior cache access activity for data from a memory address, which is indicative of the data's “usefulness.” Based on the cache control information, the predictive adjustment circuit controls generation of retention ranks for data in the cache lines when the data is inserted, accessed, and evicted. After the data has been evicted from the cache memory and is later accessed by a subsequent memory request, the persistently stored cache control information corresponding to that memory address increases the information available for determining the usefulness of data.

A cache management circuit that includes a predictive adjustment circuit configured to predictively generate cache control information based on a cache hit-miss indicator and the retention ranks of accessed cache lines to improve cache efficiency is disclosed. The predictive adjustment circuit stores the cache control information persistently, independent of whether the data remains in cache memory. The stored cache control information is indicative of prior cache access activity for data from a memory address, which is indicative of the data's “usefulness.” Based on the cache control information, the predictive adjustment circuit controls generation of retention ranks for data in the cache lines when the data is inserted, accessed, and evicted. After the data has been evicted from the cache memory and is later accessed by a subsequent memory request, the persistently stored cache control information corresponding to that memory address increases the information available for determining the usefulness of data.

Provided herein are biological information pattern (BIP) arrays and related methods for reading out information stored in a biological medium. In this manner, encoded digital information in biomolecular medium can be used as a high data density storage medium that may be read-out and accessed in a label-free manner.