A method can include: receiving, in a memory device, a read request from a host device that is coupled to the memory device by an interface; decoding an address of the read request that is received from the interface; decoding a command of the read request to determine whether the read request is for an aligned address operation; maintaining the decoded address without modification when the read request is determined as being for the aligned address operation regardless of an actual alignment of the decoded address; and executing the read request as the aligned address operation on the memory device by using the decoded address.

The technology disclosed herein pertains to a system and method for providing the ability for a computational storage device (CSD) to understand data layout based upon automatic detection or host identification of the file system occupying a non-volatile memory express (NVMe) namespace, the method including receiving, at a CSD, a request to process a file using a computation program stored on the CSD, detecting a filesystem associated with the file within a namespace of CSD, mounting the filesystem on the CSD, interpreting a data structure associated with the file within the namespace, and reading the physical data blocks associated with the file into a computational storage memory (CSM) of the CSD.

A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.

A storage system. In some embodiments, the storage system includes a plurality of object stores, and a plurality of data managers, connected to the object stores. The plurality of data managers may include a plurality of processing circuits. A first processing circuit of the plurality of processing circuits may be configured to process primarily input-output operations, and a second processing circuit of the plurality of processing circuits may be configured to process primarily input-output completions.

A multi-function device is disclosed. A first port may be used to communicate with a host processor. A second port may be used to communicate with a storage device. A third port may be used to communicate with a computational storage unit. Circuit may be used to route a message from the host processor to at least one of the storage device or the computational storage unit.

A method for memory access may include receiving, at a device, a first memory access request for a parallel workload, receiving, at the device, a second memory access request for the parallel workload, processing, by a first logical device of the device, the first memory access request, and processing, by a second logical device of the device, the second memory access request. Processing the first memory access request and processing the second memory access request may include parallel processing the first and second memory access requests. The first logical device may include one or more first resources. The method may further include configuring the first logical device based on one or more first parameters of the parallel workload. The method may further include allocating one or more first resources to the first logical device based on at least one of the one or more first parameters of the parallel workload.

Disclosed in some examples are methods, systems, and machine readable mediums that provide increased bandwidth caches to process requests more efficiently for more than a single address at a time. This increased bandwidth allows for multiple cache operations to be performed in parallel. In some examples, to achieve this bandwidth increase, multiple copies of the hit logic are used in conjunction with dividing the cache into two or more segments with each segment storing values from different addresses. In some examples, the hit logic may detect hits for each segment. That is, the hit logic does not correspond to a particular cache segment. Each address value may be serviced by any of the plurality of hit logic units.

Memory devices, systems and methods are described, such as those including a dynamically configurable channel depth. Devices, systems and methods are described that adjust channel depth based on hardware and/or software requirements. One such device provides for virtual memory operations where a channel depth is adjusted for the same physical memory region responsive to requirements of different memory processes.

A method of performing a garbage collection operation on a source block includes: performing a plurality of partial page clean operations during a series of host write operations. Each partial clean operation includes: performing a validity check process within a partitioned searching range of the source block to obtain valid page information; and performing a page clean process according to the valid page information and a target clean page number to read valid pages indicated by the valid page information.