Enabling communication between multiple storage controllers and a single-ported storage device, including determining, by an arbiter, that a first storage system controller of a plurality of storage system controllers has gained exclusive access to a single-ported storage device having a plurality of lanes; and in response to the determination, enabling communication between the first storage system controller and the storage device; and preventing communication between the storage device and at least one other storage system controller of the plurality of storage system controllers.

An adaptive memory expansion scheme is proposed, where one or more memory expansion capable Hosts or Accelerators can have their memory mapped to one or more memory expansion devices. The embodiments below describe discovery, configuration, and mapping schemes that allow independent SCM implementations and CPU-Host implementations to match their memory expansion capabilities. As a result, a memory expansion host (e.g., a memory controller in a CPU or an Accelerator) can declare multiple logical memory expansion pools, each with a unique capacity. These logical memory pools can be matched to physical memory in the SCM cards using windows in a global address map. These windows represent shared memory for the Home Agents (HAs) (e.g., the Host) and the Slave Agent (SAs) (e.g., the memory expansion device).

Systems and methods are provided for efficiently performing processing intensive operations, such as those involving large volumes of data, that enable accelerated processing time of these operations. In at least one embodiment, a system includes a graphics processor unit (GPU) including a memory and a plurality of cores. The plurality of cores perform a plurality of data analytics operations on a respectively allocated portion of a dataset, each of the plurality of cores using only the memory to store data input for each of the plurality of data analytics operations performed by the plurality of cores. The data storage for the plurality of data analytics operations performed by the plurality of cores is also provided solely by the memory.

A data processing system includes a compute blade generating a write command to store data and a read command to read the data, and a memory blade. The compute blade has a memory that stores information about performance characteristics of each of a plurality of memories, and determines priority information through which eviction of a cache line is carried out based on the stored information.

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

Systems and methods are disclosed for fused processing of a continuous mathematical operator. Fused processing of continuous mathematical operations, such as pointwise non-linear functions without storing intermediate results to memory improves performance when the memory bus bandwidth is limited. In an embodiment, a continuous mathematical operation including at least two of convolution, upsampling, pointwise non-linear function, and downsampling is executed to process input data and generate alias-free output data. In an embodiment, the input data is spatially tiled for processing in parallel such that the intermediate results generated during processing of the input data for each tile may be stored in a shared memory within the processor. Storing the intermediate data in the shared memory improves performance compared with storing the intermediate data to the external memory and loading the intermediate data from the external memory.

A semiconductor device capable of shortening a time required for data transfer and data organizing is provided. The solid state device includes a processor, a memory, an external interface, registers for storing data received by the external interface, a mirror register buffer, a processor, a memory, an external interface, registers, and an internal bus connected to the mirror register buffer. Registers output data to the mirror register buffer without going through the internal bus. Mirror register buffer gives the data input from the registers an address in a mirror register buffer different from the address allocated to the register, and transfers the data to the memory without passing through the internal bus.

The present disclosure relates to systems, methods, and computer-readable media for data from a first multi-dimensional memory block to a second multi-dimensional memory block. For example, systems described herein facilitate transferring data between memory blocks having different shapes from one another. The systems described herein facilitate transferring data between different shaped memory blocks by identifying shape properties and other characteristics of the data and generating a plurality of network packets having control data based on the identified shape properties and other characteristics. This data included within the network packets enables memory controllers to determine memory addresses on a destination memory block to write data from the network packets. Features described herein facilitate efficient transfer of data without generating a linearized copy that relies on constant availability of significant memory resources.

The present application relates to a data processing method for a numerical control system, a computer device and a storage medium. The method comprises: receiving a data request, the data request carrying a target data identifier; parsing the data request to obtain an interactive type corresponding to the target data identifier; when the interactive type corresponding to the target data identifier is a type corresponding to real-time data, searching for data corresponding to the target data identifier in a shared memory of the numerical control system; transferring the data corresponding to the target data identifier from the shared memory to a data cache of the numerical control system and outputting the data.

A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.