An apparatus includes an output bus configured to store data, a match table, one or more storage devices, and logic. The match table is configured to store a plurality of entries, each entry including a key value, wherein the match table specifies a matching entry in response to being queried by the query data. The one or more storage devices are configured to store operation information for each of the plurality of entries stored in the match table. The operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table. The logic is configured to receive one or more operands from the output bus, identify one or more instructions from the one or more storage devices, and generate, based on the one or more instructions and the one or more operands, processed data.

An apparatus includes an output bus configured to store data, a match table, one or more storage devices, and logic. The match table is configured to store a plurality of entries, each entry including a key value, wherein the match table specifies a matching entry in response to being queried by the query data. The one or more storage devices are configured to store operation information for each of the plurality of entries stored in the match table. The operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table. The logic is configured to receive one or more operands from the output bus, identify one or more instructions from the one or more storage devices, and generate, based on the one or more instructions and the one or more operands, processed data.

In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

A processing system comprises a control bus and a plurality of logic units. The control bus is configurable by configuration data to form signal routes in a control barrier network coupled to processing units in an array of processing units. The plurality of logic units has inputs and outputs connected to the control bus and to the array of processing units. A logic unit in the plurality of logic units is operatively coupled to a processing unit in the array of processing units and is configurable by the configuration data to consume source tokens and a status signal from the processing unit on the inputs and to produce barrier tokens and an enable signal on the outputs based on the source tokens and the status signal on the inputs.

An adaptation method between PCIE and SPI realized based on FPGA, comprising following steps: S01: a PCIE equipment sends PCIE information to a mapping module through a PCIE module; S02: the mapping module extracts SPI information from the PCIE information and transmits the SPI information to a SPI equipment through an SPI module; all of the PCIE module, the mapping module and the SPI module are located on a FPGA chip; S03: the SPI equipment performs a read/write operation according to the SPI information, and feeds back SPI operation information subjected to the read/write operation to the mapping module; S04: the mapping module modifies PCIE information according to the SPI operation information to obtain PCIE feedback information; S05: the PCIE equipment reads the PCIE feedback information through the PCIE module. The present invention provides a conversion adapter and a method between PCIE and SPI realized based on FPGA to realize conversion for a PCI interface and a SPI interface, so as to perform a read/write operation of an AD chip with the SPI interface or a DA chip with the SPI interface, which has universal applicability.

A method of reading data includes: receiving a digital signal, wherein the digital signal includes a sync signal and a data signal; performing an oversampling operation to the digital signal, and calculating a plurality of sampling points according to the oversampling operation; by a first counter counting the sampling points to obtain a first count value; based on the first count value defining a second count value; defining a unit interval; in the unit interval, defining a data reading range; and in the data reading range, reading the data signal corresponding to data of the unit interval as a first value when a potential of each of the sampling points counted is changed from a first potential to a second potential.

A secondary processor device ownership assignment system includes a chassis that houses devices, a secondary processing system, a central processing system that includes an integrated switch device that is coupled to each of the devices and the secondary processing system, and a device ownership subsystem that is coupled to the central processing system. The device ownership system accesses device information for a subset of the devices that will be owned by the secondary processing system, and configures the device information for the subset of the devices such that the subset of the devices are hidden from an operating system provided by the central processing system. The secondary processing system reconfigures the device information for the subset of the plurality of devices such that the subset of the plurality of devices are accessible by the secondary processing system.

A secondary processor device ownership assignment system includes a chassis that houses devices, a secondary processing system, a central processing system that includes an integrated switch device that is coupled to each of the devices and the secondary processing system, and a device ownership subsystem that is coupled to the central processing system. The device ownership system accesses device information for a subset of the devices that will be owned by the secondary processing system, and configures the device information for the subset of the devices such that the subset of the devices are hidden from an operating system provided by the central processing system. The secondary processing system reconfigures the device information for the subset of the plurality of devices such that the subset of the plurality of devices are accessible by the secondary processing system.

In accordance with an embodiment, an electronic device includes a secure element configured to implement a plurality of operating systems; and a near field communication module coupled to the secure element by a single bus and by a routing circuit configured to route routing data between the plurality of operating systems and a receive circuit of the near field communication module.