A method for integrating a further bus subscriber into a bus system, and a bus system, having a master module and subscribers disposed in series, includes the temporally consecutive method steps: in a first method step, the further bus subscriber transmits a data packet to the master module in order to log in to the master module, in a second method step, a bus subscriber disposed between the further bus subscriber and the master module stops the data packet and checks whether the bus system has already received a release, in a third method step, the first bus subscriber forwards the data packet to the master module if the bus system has not yet received a release, or in a third, in particular an alternative, method step, if the bus system has already received a release, the bus subscriber stores the data packet and waits until the release of the bus system is revoked and after the release has been revoked, forwards the stored data packet to the master module.

A method for integrating a further bus subscriber into a bus system, and a bus system, having a master module and subscribers disposed in series, includes the temporally consecutive method steps: in a first method step, the further bus subscriber transmits a data packet to the master module in order to log in to the master module, in a second method step, a bus subscriber disposed between the further bus subscriber and the master module stops the data packet and checks whether the bus system has already received a release, in a third method step, the first bus subscriber forwards the data packet to the master module if the bus system has not yet received a release, or in a third, in particular an alternative, method step, if the bus system has already received a release, the bus subscriber stores the data packet and waits until the release of the bus system is revoked and after the release has been revoked, forwards the stored data packet to the master module.

Examples are described herein for dynamically allocating shared bus lanes provided by a peripheral component bridge. A multiplexor may be operably coupled with the bridge via the shared bus lanes. A plurality of peripheral component slots may each be operably coupled with the multiplexor via a respective plurality of peripheral bus lanes. The multiplexor may multiplex the shared bus lanes to multiple different peripheral component slots. Circuitry may: interrogate each of the peripheral component slots to obtain information about a modular component installed in the peripheral component slot, wherein the information about the modular component includes a usable range of bus lanes and a transmission speed capability; and cause the multiplexor to dynamically allocate the number of shared bus lanes to the respective pluralities of peripheral bus lanes of the peripheral component slots based on the usable ranges and transmission speed capabilities of the installed modular components.

Examples are described herein for dynamically allocating shared bus lanes provided by a peripheral component bridge. A multiplexor may be operably coupled with the bridge via the shared bus lanes. A plurality of peripheral component slots may each be operably coupled with the multiplexor via a respective plurality of peripheral bus lanes. The multiplexor may multiplex the shared bus lanes to multiple different peripheral component slots. Circuitry may: interrogate each of the peripheral component slots to obtain information about a modular component installed in the peripheral component slot, wherein the information about the modular component includes a usable range of bus lanes and a transmission speed capability; and cause the multiplexor to dynamically allocate the number of shared bus lanes to the respective pluralities of peripheral bus lanes of the peripheral component slots based on the usable ranges and transmission speed capabilities of the installed modular components.

The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.

The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.

An apparatus includes an interface circuit adapted to couple the apparatus to a serial bus, a slot counter, and a processor. The slot counter may be configured to monitor a radio frequency coexistence management cycle that includes a plurality of time slots. The processor may be configured to transmit a first datagram through the interface circuit during a first time slot in the plurality of time slots. The apparatus may be uniquely permitted to initiate transactions over the serial bus during the first time slot. The processor may be further configured to participate in an arbitration procedure during a second time slot in the plurality of time slots. More than one device coupled to the serial bus may be permitted to initiate transactions in the second time slot.

A system component having a configurable communication behavior. The system component includes at least one interface for a data bus for the communication with at least one further system component. A defined communications protocol for the transmitting and receiving of data and bus commands is used on the data bus. The communications protocol provides that the at least one further system component queries the communication behavior of the system component via the data bus to adapt its own communication behavior to that of the system component. The system component includes a register for configuration data that define the communication behavior of the system component on the data bus, the register being connected to the data bus so that the configuration data stored in the register are available on the data bus. The function scope of the system component allows for different communication behaviors.

A system component having a configurable communication behavior. The system component includes at least one interface for a data bus for the communication with at least one further system component. A defined communications protocol for the transmitting and receiving of data and bus commands is used on the data bus. The communications protocol provides that the at least one further system component queries the communication behavior of the system component via the data bus to adapt its own communication behavior to that of the system component. The system component includes a register for configuration data that define the communication behavior of the system component on the data bus, the register being connected to the data bus so that the configuration data stored in the register are available on the data bus. The function scope of the system component allows for different communication behaviors.

Systems and methods for load detection on serial communication data lines are provided herein. In certain configurations, a serial communication system includes a data line having a load capacitance and a master device configured to generate a command signal for a slave device to measure the load capacitance on the data line. The system further includes a slave device including a load detector including a controller configured to receive the command signal from the master device, provide a first fixed current to the data line, determine an amount of time elapsed while the data line is driven to a first threshold value, and determine the load capacitance of the data line based on the amount of time elapsed.