A method can include receiving network packets including forwarding plane packets; evaluating header information of the network packets to map network packets to any of a plurality of destinations on the module, each destination corresponding to any of a plurality of services executed by offload processors of the module; configuring operations of the offload processors; and in response to forwarding plane packets, executing operations on the forwarding plane packets; wherein the receiving, evaluation and processing of the forwarding plane packets are performed independent of the host processor. Corresponding systems and methods are also disclosed.

A method can include receiving network packets including forwarding plane packets; evaluating header information of the network packets to map network packets to any of a plurality of destinations on the module, each destination corresponding to any of a plurality of services executed by offload processors of the module; configuring operations of the offload processors; and in response to forwarding plane packets, executing operations on the forwarding plane packets; wherein the receiving, evaluation and processing of the forwarding plane packets are performed independent of the host processor. Corresponding systems and methods are also disclosed.

A method for controlling the sending of data by a plurality of processors belonging to a device, the method comprising: sending a first message to a first processor of the plurality of processors to grant permission to the first processor of the plurality of processors to send a first set of data packets over at least one external interface of the device; receiving from the first processor, an identifier of a second processor of the plurality of processors; and in response to receipt of the identifier of the second processor, send a second message to the second processor to grant permission to the second processor to send a second set of data packets over the at least one external interface.

A method for controlling the sending of data by a plurality of processors belonging to a device, the method comprising: sending a first message to a first processor of the plurality of processors to grant permission to the first processor of the plurality of processors to send a first set of data packets over at least one external interface of the device; receiving from the first processor, an identifier of a second processor of the plurality of processors; and in response to receipt of the identifier of the second processor, send a second message to the second processor to grant permission to the second processor to send a second set of data packets over the at least one external interface.

A queuing requester for access to a memory system is provided. Transaction requests are received from two or more requestors for access to the memory system. Each transaction request includes an associated priority value. A request queue of the received transaction requests is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system is performed using the selected priority value.

Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.

Embodiments using a distributed bus arbiter for one cycle channel selection with inter-channel ordering constraints. A distributed bus arbiter that orders one or more memory bus transactions originating from a plurality of master bus components to a plurality of shared remote slaves over shared serial channels attached to differing interconnect instances may be implemented.

Embodiments using a distributed bus arbiter for one cycle channel selection with inter-channel ordering constraints. A distributed bus arbiter that orders one or more memory bus transactions originating from a plurality of master bus components to a plurality of shared remote slaves over shared serial channels attached to differing interconnect instances may be implemented.

A programmable slave circuit on a communication bus is provided. In a non-limiting example, the communication bus can be a radio frequency front-end (RFFE) bus operating based on a master-slave topology and the programmable slave circuit can be an RFFE slave circuit on the RFFE bus. The programmable slave circuit is configured to receive a high-level command(s) (e.g., a macro word) over the communication bus. A processing circuit in the programmable slave circuit is programmed to generate a low-level command(s) (e.g., a bitmap word) for controlling a coupled circuit(s) based on the high-level command(s). In this regard, it is possible to program or reprogram the processing circuit, for example via over-the-air (OTA) updates, based on the high-level command(s) to be supported, thus making it possible to flexibly customize the programmable slave circuit according to operating requirements and configurations.

A programmable slave circuit on a communication bus is provided. In a non-limiting example, the communication bus can be a radio frequency front-end (RFFE) bus operating based on a master-slave topology and the programmable slave circuit can be an RFFE slave circuit on the RFFE bus. The programmable slave circuit is configured to receive a high-level command(s) (e.g., a macro word) over the communication bus. A processing circuit in the programmable slave circuit is programmed to generate a low-level command(s) (e.g., a bitmap word) for controlling a coupled circuit(s) based on the high-level command(s). In this regard, it is possible to program or reprogram the processing circuit, for example via over-the-air (OTA) updates, based on the high-level command(s) to be supported, thus making it possible to flexibly customize the programmable slave circuit according to operating requirements and configurations.