Embodiments using a distributed bus arbiter for one cycle channel selection with inter-channel ordering constraints. A distributed bus arbiter that orders one or more memory bus transactions originating from a plurality of master bus components to a plurality of shared remote slaves over shared serial channels attached to differing interconnect instances may be implemented.

In a multi-cloud computing environment comprising a plurality of cloud platforms, wherein one cloud platform is a source of a model and a data set and further wherein the model is to be executed against the data set on one or more of the other cloud platforms, the method maintains a decentralized architecture comprising a file system and a message bus, wherein the file system comprises a plurality of decentralized file system nodes corresponding to the plurality of cloud platforms, and the message bus comprises a plurality of decentralized message bus nodes corresponding to the plurality of cloud platforms. Further, the method manages sharing of the model and the data set via at least a portion of the decentralized file system nodes and manages messaging related to execution of the model against the data set via at least a portion of the decentralized message bus nodes.

In a multi-cloud computing environment comprising a plurality of cloud platforms, wherein one cloud platform is a source of a model and a data set and further wherein the model is to be executed against the data set on one or more of the other cloud platforms, the method maintains a decentralized architecture comprising a file system and a message bus, wherein the file system comprises a plurality of decentralized file system nodes corresponding to the plurality of cloud platforms, and the message bus comprises a plurality of decentralized message bus nodes corresponding to the plurality of cloud platforms. Further, the method manages sharing of the model and the data set via at least a portion of the decentralized file system nodes and manages messaging related to execution of the model against the data set via at least a portion of the decentralized message bus nodes.

A storage apparatus includes a plurality of control devices configured to control access a plurality of storage devices, and a relay apparatus including a plurality of coupling devices, each of which is configured to couple the control devices so as to be communicable with each other. The relay apparatus includes, for each coupling device, a monitoring controller configured to perform monitoring of the relay apparatus. A first monitoring controller provided in a first coupling device from among the coupling devices notifies, when the first monitoring controller detects an abnormal state in the relay apparatus, a first control device from among the control devices of information relating to the abnormal state detected by the first monitoring controller. The first control device performs a decoupling process that decouples an abnormal part from the relay apparatus based on the information relating to the abnormal state received from the first monitoring controller.

In a system in which a plurality of information processing devices that access data stored in one device according to individual clocks are connected, and data regarding access from another device flows through a path relaying the plurality of information processing devices, a data transfer control system that increases data transfer performance between the information processing devices is disclosed. The data transfer control system is provided with: a synchronization control unit that, when a first information processing device obtains reply data by using a communication path sequentially relayed by a plurality of second information processing devices when accessing any of the second information processing devices that access the stored data in the first information processing device in synchronism with the individual clock signals, outputs the reply data generated in synchronism with the individual clock signals in synchronism with a common clock signal for each of the second information processing devices; and a reply transmission means that stores the reply data, output from the synchronization control unit in synchronism with the common clock signal, for a predetermined time and that then transmits the reply data to the second information processing device of the later stage.

Asynchronous event-based start of input/output operations is implemented in a distributed system. Within the distributed system, each master device—of a plurality of master devices coupled to a respective plurality of slave devices via an internal network—may implement one or more timed-functions configured to control timing of physical input operations and/or physical output operations for the respective plurality of slave devices, and streams between the master device and the respective plurality of slave devices. A subset of the slave devices may be further interconnected via a shared signal-based bus, which may be used to propagate an asynchronous event that may be used to start at least one of the one or more timed functions implemented on a master device coupled to at least one slave device of the subset of slave devices. The asynchronous event may be generated by one of the slave devices.

Asynchronous event-based start of input/output operations is implemented in a distributed system. Within the distributed system, each master device—of a plurality of master devices coupled to a respective plurality of slave devices via an internal network—may implement one or more timed-functions configured to control timing of physical input operations and/or physical output operations for the respective plurality of slave devices, and streams between the master device and the respective plurality of slave devices. A subset of the slave devices may be further interconnected via a shared signal-based bus, which may be used to propagate an asynchronous event that may be used to start at least one of the one or more timed functions implemented on a master device coupled to at least one slave device of the subset of slave devices. The asynchronous event may be generated by one of the slave devices.

A data processing device includes a first sub-arbiter configured to arbitrate an access by first and second masters that access data stored in a memory; a second sub-arbiter configured to arbitrate an access to the memory by a plurality of masters other than the first and the second masters; a main arbiter configured to prioritize the access to the memory by the first sub-arbiter over the access to the memory by the second sub-arbiter; and a limiting unit configured to limit an amount of the access to the memory by the second master within a preset range.

A semiconductor device is configured so that two or more master devices access a slave device via a bus. The semiconductor device includes: a priority generation circuit that generates a priority based on a transfer amount between a specific master device and a specific slave device; and an arbitration circuit that performs an arbitration based on the priority when competition of the accesses occurs.

A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.