The present invention is directed to a docking station system. The docking station system includes a housing that is constructed from outer walls. The housing defines a first compartment, a second compartment, and a third compartment. The docking station system further includes docking station circuitry disposed in the first compartment, one or more battery modules disposed in the second compartment, and uninterruptible power supply (UPS) circuitry disposed in the third compartment. The aforementioned UPS circuitry and docking station circuitry cooperate to enable certain functionalities. The certain functionalities can be one or more of smart shutdown, load shedding, or remote management functions.

A variable power bus (VPB) cable, such as a USB Type-C cable, is validated for actual current capacity with respect to a specified power rating for the cable. The power cable validation is performed when the cable is connected to a power storage adapter and a portable information handling system. The validation includes, prior to negotiating a power delivery contract for electrical power to be supplied to the information handling system from the VPB port via the VPB cable, applying a first voltage to the VPB cable to identify a first indication of a current capacity of the VPB cable; and when the first indication confirms that the current capacity of the VPB cable corresponds to a specified power rating for the VPB cable, enabling the power delivery contract to be negotiated according to the specified power rating, otherwise blocking the power delivery contract using the VPB cable.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

Framework for network bypass is disclosed herein. Exemplary network bypass apparatus may include a relay, a first connection interface connectable to a network device, a second connection interface connectable to a first communication device, and a third connection interface connectable to a second communication device. The network bypass apparatus may further include a housing enclosing the relay and the first, second and third connection interfaces, wherein the relay communicatively couples the first connection interface and the third connection interface while communicatively decoupling the first connection interface and the second connection interface in response to disconnection of power to the relay during a bypass mode.

Apparatus, systems and methods for implementing delayed decompression schemes. As a burst of packets comprising compressed packets and uncompressed packets are received over an interconnect link, they are buffered in a receive buffer without decompression. Subsequently, the packets are forwarded from the receive buffer to a consumer such as processor core, with the compressed packets being decompressed prior to reaching the processor core. Under a first delayed decompression approach, packets are decompressed when they are read from the receive buffer in conjunction with forwarding the uncompressed packet (or uncompressed data contained therein) to the consumer. Under a second delayed decompression scheme, the packets are read from the receive buffer and forwarded to a decompressor using a first datapath width matching the width of the packets, decompressed, and then forwarded to the consumer using a second datapath width matching the width of the uncompressed data.

The present disclosure is directed to improving compatibility between chiplets integrated with disparate chiplet interfaces. To reduce compatibility issues due non-matching bump maps, a dual-mode bump map assignment may be implemented to enable a chiplet to utilize multiple signal number sequence assignments. Additionally, a modularized Advanced Interface Bus (AIB) interface may be implemented to reduce channel mismatch in AIB -UCIe multi-channel interoperability.

A control system is for controlling safety-critical processes, non-safety-critical processes, and/or installation components. The control system includes: at least one control unit configured to control non-safety-critical processes and/or non-safety-critical installation components, at least one safety control unit for controlling safety-critical processes and/or safety-critical installation components, and at least one input/output unit connected to the first control unit via an internal input/output bus. The control system is configured to act as communication master or as communication minion or as both in a pool having other devices that is connected via field bus, and to that end, the control system includes a master communication coupler and a minion communication coupler. The control system is modularly configurable. At least the safety control unit includes respective subunits with master functionality and subunits with minion functionalities.

A terminal includes a security subsystem, a baseband processor, and a first bidirectional bus coupled between the security subsystem and the baseband processor. The security subsystem is configured to manage at least one of data related to a user identity and data related to network security in wireless communication, and exchange the data with the baseband processor by using the first bidirectional bus. The baseband processor is configured to exchange the data with the security subsystem by using the first bidirectional bus, and implement wireless communication by using the data. The security subsystem and the baseband processor are in the same hierarchy. The security subsystem may proactively perform data transmission by using the first bidirectional bus.

A single-level single-line full-duplex bus communication method and system are disclosed. The method includes: transmitting, by a first signal transceiver, data according to a first internal transmitter clock F1, simultaneously monitoring a level change on a bus, and parsing received data; transmitting, by a second signal transceiver, data according to a second internal transmitter clock F2, simultaneously monitoring the level change on the bus, and parsing received data; and communicating between the first and second signal transceivers by means of a single line, wherein the first and second transmitter clocks satisfy a relationship: F1>F2*(length of data unit+2). The system achieves single-level single-line full-duplex communication by using different coding formats and different internal transmitter clocks, whereby the number of signal lines can be reduced, single-level communication can be achieved by using universal digital levels, i.e., 0, 1, and the hardware implementation difficulty can be reduced.

The present disclosure provides an interconnect for a non-uniform memory architecture platform to provide remote access where data can dynamically and adaptively be compressed and decompressed at the interconnect link. A requesting interconnect link can add a delay to before transmitting requested data onto an interconnect bus, compress the data before transmission, or packetize and compress data before transmission. Likewise, a remote interconnect link can decompress request data.