A memory manager disposed between a memory and a processor. One end of the memory manager is coupled to the processor using a serial line, and the other end of the memory manager is coupled to the memory using a parallel line to provide the processor with a serial interface instead of a parallel interface.

A electronic device includes a plurality of first photosensitive chips, one first fusion chip, and one processing chip. Each first photosensitive chip is connected to the first fusion chip by a respective data transmission channel and is configured both to generate a MIPI protocol-based data stream and to transmit said data stream to the first fusion chip by the respective data transmission channel. The first fusion chip is connected to the processing chip by a data transmission channel and is configured to converge data streams received via a plurality of data transmission channels connected to the plurality of first photosensitive chips, to obtain a first high-speed convergent data, and to send the first high-speed convergent data to the processing chip. The processing chip is configured to receive the high-speed convergent data stream and obtain an image by using the received data stream.

A method for supporting TCM communication by a BIOS of an ARM server, including: setting an access mode of a LPC bus device to a 4-byte mode by means of a BIOS of an ARM server; causing the BIOS to perform data communication with a TCM chip of the LPC bus device in the 4-byte mode; in response to the BIOS reading a register by means of the LPC bus device, determining a type of the register; in response to determining that the type of the register is a specific FIFO register, changing a control register from the 4-byte mode to a single-byte mode, and performing single-byte read-write on the specific FIFO register; and in response to completion of read-write of the specific FIFO register, changing the control register to the 4-byte mode by means of the BIOS, and performing a read-write operation on other FIFO registers.

In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current.

In a second embodiment an offline charge pump utilizes a switching matrix to recombine capacitors in accordance with the voltage on the AC half wave and then in accordance with a desired output voltage to feed a load, such that said recombinations occur at a frequency much higher than the frequency of the AC rectified half wave such that charge is “pumped” from the input at one voltage to the output at another voltage through the AC halfwave while providing a constant output voltage to the load.

A multi-chip system and a data transmission method thereof are provided. The multi-chip system includes a first chip, a link unit, and a second chip. The first chip includes multiple transmitter (TX) channels and a first data processing module. The TX channels are configured to provide at least one transaction information. The first data processing module converts the at least one transaction information into at least one first data packet according to a general packet format and packs the at least one first data packet according to a specific packet format to generate a second data packet. The first data processing module merges two sets of second data packets into a third data packet and transmits the third data packet to the link unit. The second chip receives the third data packet through the link unit.

In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.

A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.

A semiconductor memory device includes a substrate that has a first main surface and a second main surface opposite to the first main surface, a first semiconductor chip which is mounted on the first main surface and includes a first register, a plurality of first input/output (IO) terminals, and a first circuit connected between the first IO terminals and the first register, and a second semiconductor chip which is mounted on the second main surface and includes a second register, a plurality of second input/output (IO) terminals, and a second circuit connected between the second IO terminals and the second register. The second circuit is connected to the second IO terminals through input lines and to the second register through output lines, and is configured to change a connection path between the input lines and the output lines in response to a connection change command.

Described herein is a modular parallel processor comprising an active base die including hardware logic, interconnect logic, and a plurality of chiplet slots and a plurality of chiplets vertically stacked on the active base die and coupled with the plurality of chiplet slots of the active base die. The plurality of chiplets is interchangeable during assembly of the modular parallel processor and include a group of hardware logic chiplets having a plurality of different functional units and a group of memory chiplets having a plurality of different memory devices. The hardware logic chiplets and the memory chiplets interconnect via the interconnect logic within the active base die.

An interface for coupling an agent to a fabric supports a load/store interconnect protocol and includes a header channel implemented on a first subset of a plurality of physical lanes, the first subset of lanes including first lanes to carry a header of a packet based on the interconnect protocol and second lanes to carry metadata for the header. The interface additionally includes a data channel implemented on a separate second subset of the plurality of physical lanes, the second subset of lanes including third lanes to carry a payload of the packet and fourth lanes to carry metadata for the payload.