Embodiments of the present disclosure include techniques for transferring non-power of two (2) bytes of data between modules of an integrated circuit over an on-chip communication fabric. In one embodiment, the present disclosure includes an on-chip communication fabric, a first module comprising an interface coupled to the fabric having a first data width, and a second module comprising an interface coupled to the fabric having a second data width smaller than the first data width. The non-power of two (2) bytes of data are sent between the first and second modules through the fabric, and the fabric maps the non-power of two (2) bytes of data between the first and second data widths.

An interface circuit is provided, which includes an interface, a detection control module, a switch module, a first data line, and a second data line. A width of the second data line is smaller than that of the first data line, the interface is electrically connected to the detection control module and a movable end of the switch module, a first fixed end and a second fixed end of the switch module are electrically connected to the first data line and the second data line, respectively. When the detection control module detects that a signal of the interface is a power supply signal, the movable end of the switch module is connected to the first fixed end; when the detection control module detects that a signal of the interface is a data signal, the movable end of the switch module is connected to the second fixed end.

A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.

A chip module has a plurality of first ports, at least some or all of the first ports are first selection ports, and each first selection port may act as a write port or a read port. The chip module further includes a first control module. The first control module controls, based on a transmit/receive requirement of the chip module, the first selection port to be switched to a read port or a write port, to match the transmit/receive requirement of the chip module. The first selection port may selectively act as a read port or a write port, so that switching can be performed based on an operating state of the chip module, increasing a read/write bandwidth. The first control module controls an operating state of the first selection port, to flexibly adjust a quantity of read ports and a quantity of write ports of the chip module.

A data transmission method, applied to a data transmission system comprising a reception interface and a plurality of transmission interfaces, comprising: (a) receiving first transmission information from a source device via the reception interface, wherein the first transmission information comprises information of data groups corresponding to at least two of the transmission interfaces; and (b) transmitting at least portion of the data groups by a corresponding one of the transmission interfaces in turn to a target device which corresponds to the data group comprising the portion, according to the first transmission information, until transmission of all of the data groups is completed.

The present disclosure relates to a communication device, a communication method, and a program for offering adaptability to a wider variety of applications and enhancing reliability of communications.

With a CCI protocol implemented as an upper layer, a physical layer transmits and receives data including an extended header and an extended footer to and from another communication device. A CCI-FS processing section compares a Desination ID included in the extended header with an ID (Source ID) given to the communication device, and determines whether or not the data is for accessing the communication device. The physical layer is MIPI A-PHY that has an asymmetrical upper layer of a point-to-point topology and is designed to allow high-speed data transmission, control data, and electric power to share one physical wire. The present technology is applicable to a communication system that is used for connection in an in-vehicle camera, for example.

A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.

Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16 KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4 KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.

A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs). The first transmission bus coupled to the type memory cell array group has a first programmable transmitting or receiving data rate, a first programmable transmitting or receiving signal swing, a first programmable bus width, and a combination thereof. The logic unit is coupled to the first transmission bus for accessing the type memory cell array group through the first transmission bus.