An electronic device includes a bus driver and circuitry. The bus driver is coupled to a parallel bus including N data lines. The circuitry is configured to receive a data unit for transmission over the N data lines, to determine a first count indicative of a number of data bits in the data unit having a predefined value, and a second count indicative of a number of inverted data bits relative to corresponding bits in a previously transmitted data unit, to make a decision of whether to invert the data unit based on the first and second counts, depending on whether such inversion is expected to reduce power consumption of transmitting the data unit over the bus, to produce an output data unit by retaining or inverting the data unit based on the decision, and to transmit the output data unit over the data lines via the bus driver.

A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

Disclosed is an electronic device including: a USB connector connected to a USB plug of an external device; a high-speed interface; a voltage source for supplying a voltage to the high-speed interface; a first circuit portion connected to a ground portion, and has a second impedance higher than a first impedance of the high-speed interface; and a processor. The processor is configured to monitor the external device by using the high-speed interface in a first interval of a first frame, form a disconnection sensing path by forming a connection between the first circuit portion and a second circuit portion of the external device, and use the disconnection sensing path to determine whether the connection between the USB connector and the USB plug has been disconnected. The second circuit portion may have a fourth impedance higher than a third impedance of an external high-speed interface. Various other embodiments are also possible.

An audio system includes a base station, an interface that enables transmission of audio content from a handheld media device to the base station via a cable, and one or more remote speakers configured to receive the audio content from the base station. The base station includes a housing, a speaker integrated within the housing to produce an audible signal from the audio content provided by the handheld media device, and a transceiver integrated within the housing for wirelessly transmitting the audio content to the one or more remote speakers. The one or more remote speakers are configured to wirelessly relay the audio content, thereby to supply the audio content beyond the transmission range of the transceiver.

Systems and methods for load detection on serial communication data lines are provided herein. In certain configurations, a serial communication system includes a data line having a load capacitance and a master device configured to generate a command signal for a slave device to measure the load capacitance on the data line. The system further includes a slave device including a load detector including a controller configured to receive the command signal from the master device, provide a first fixed current to the data line, determine an amount of time elapsed while the data line is driven to a first threshold value, and determine the load capacitance of the data line based on the amount of time elapsed.

The present invention discloses a USB signal output circuit having reverse current prevention mechanism. A switch circuit turns on when a switch control terminal receives a first high level voltage to output a signal from a signal input terminal to a signal output terminal. A first voltage pull-low circuit includes a passive-component high-pass filter circuit and a discharging circuit. The passive-component high-pass filter circuit couples an output terminal voltage of the signal output terminal to a pull-low control terminal. The discharging circuit turns on when a voltage of the pull-low control terminal is larger than a predetermined voltage level to discharge the switch control terminal to pull the switch control terminal to a second high level voltage. A second voltage pull-low circuit pulls the switch control terminal to a low level voltage when the output terminal voltage is larger than a reference voltage and does not have a glitch.

Slave-initiated communications over a single-wire bus are described in the present disclosure. In contrast to a conventional single-wire bus apparatus wherein communications over the single-wire bus are always initiated by a master circuit, a single-wire bus apparatus disclosed herein allows a slave circuit(s) to initiate communications over the single-wire bus. More specifically, multiple slave circuits can concurrently contend for access to the single-wire bus via current mode signaling (CMS). In response to the CMS asserted by the multiple slave circuits, a master circuit provides a number of pulse-width modulation (PWM) symbols over the single-wire bus to indicate which of the multiple slave circuits is granted access to the single-wire bus. By supporting slave-initiated communications over the single-wire bus, it is possible to improve efficiency, cost, and power consumption in an electronic device (e.g., smartphone) wherein the single-wire bus apparatus is deployed.

An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

A method includes wirelessly receiving audio content via a first transceiver included in a housing of a first device and producing a first audible signal from the audio content via a speaker included in the housing of the first device. The audio content is wirelessly transmitted via the first transceiver to a second transceiver integrated within a first remote speaker. A second audible signal is produced from the audio content via the first remote speaker. The method also includes wirelessly relaying the audio content via the second transceiver to a third transceiver integrated within a second remote speaker and producing a third audible signal from the audio content via the second remote speaker. The second remote speaker is located outside of the transmission range of the first transceiver.

A system and method for efficiently transferring data between devices. In various embodiments, a host computing device receives parallel data, encodes the parallel data as a count of pulses as serial data, and conveys the serial data to a peripheral device. The peripheral device decodes the received serial data to determine the parallel data, which is sent to processing logic. The devices send the encoded pluses on a bidirectional line, so the pulses are capable of being sent in both directions. The devices send the encoded pulses on the bidirectional line using a non-zero base voltage level. The devices are capable of using a voltage headroom when conveying encoded pulses between one another. Therefore, a full voltage swing between a ground reference voltage level and a power supply voltage level is not used when conveying the encoded pulses, which reduces power consumption.