A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

Systems, apparatus and methods are provided for multi-drop multi-load NAND interface topology where a number of NAND flash devices share a common data bus with a NAND controller. A method for controlling on-die termination in a non-volatile storage device may comprise receiving a chip enable signal on a chip enable signal line from a controller, receiving an on-die termination (ODT) command on a data bus from the controller while the chip enable signal is on, decoding the on-die termination command and applying termination resistor (RTT) settings in the ODT command to a selected non-volatile storage unit at the non-volatile storage device to enable ODT for the selected non-volatile storage unit.

Systems and methods for load detection on serial communication data lines are provided herein. In certain configurations, a serial communication system includes a data line having a load capacitance and a master device configured to generate a command signal for a slave device to measure the load capacitance on the data line. The system further includes a slave device including a load detector including a controller configured to receive the command signal from the master device, provide a first fixed current to the data line, determine an amount of time elapsed while the data line is driven to a first threshold value, and determine the load capacitance of the data line based on the amount of time elapsed.

Various systems and methods for configuring a pluggable computing device are described herein. A pluggable computing device may be configured to be compatible with a pluggable host system using a default communication channel to obtain configuration settings and configure a programmable logic device on the pluggable computing device. The pluggable computing device may perform chain of trust processing on the pluggable host system. The pluggable computing device may be disposed on a compute card, which may include a heat sink in a particular configuration.

A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

In one embodiment, an apparatus includes a host controller to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto a first line of the interconnect; a second driver to drive a clock signal onto a second line of the interconnect; and a mode control circuit to cause the second driver to drive the clock signal onto the second line of the interconnect in a first mode and to cause the first driver and the second driver to drive differential information onto the first line and the second line of the interconnect in a second mode. Other embodiments are described and claimed.

Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

A system management bus link, a method and apparatus for determining the pull-up resistance thereof, and a device. The system management bus link comprises: a motherboard chip, a first pull-up resistor, and a second pull-up resistor. In the present invention, when resistance values of the first pull-up resistor and the second pull-up resistor satisfy configuring on a system management bus link any number of PSU power supplies that is smaller than or equal to a number threshold, a clock line in the link and a drive current in a data line are between a 0.5-times drive current threshold and a 0.9-times drive current threshold. Thus, the pull-up resistance of a motherboard end is optimized, which reduces the effect on the drive capacity of the number of PSU power supplies on a link, guarantees the drive capacity of the link, and improves link stability.

Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.

Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.