Systems and methods of inferential user matching include inferring an interest in matching between the first user and the second user based at least in part on a first profile of a first user and a second profile of a second user. Based at least in part on the inferred interest in matching, the systems and methods match the first user and the second user for a service, and transmit (i) a first representation of the first user to a portable device of the second user, and (ii) a second representation of the second user to a portable device of the first user.

System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.

A data processing system includes a central processing unit (CPU) and accelerator cards coupled to the CPU over a bus, each of the accelerator cards having a plurality of data processing (DP) accelerators to receive DP tasks from the CPU and to perform the received DP tasks. At least two of the accelerator cards are coupled to each other via an inter-card connection, and at least two of the DP accelerators are coupled to each other via an inter-chip connection. Each of the inter-card connection and the inter-chip connection is capable of being dynamically activated or deactivated, such that in response to a request received from the CPU, any one of the accelerator cards or any one of the DP accelerators within any one of the accelerator cards can be enabled or disabled to process any one of the DP tasks received from the CPU.

An inferential user matching system can determine a mutual interest between a first user and a second user. Based on determining the mutual interest, the system can transmit an expression of interest indication to a portable device(s) of the first and/or second user.

A data processing apparatus includes a first processing unit that executes real-time processing with respect to data, a second processing unit that executes batch processing with respect to data that is output from the first processing unit as a result of processing by the first processing unit, and a monitor that monitors a status of the processing by the first processing unit and a status of processing by the second processing unit. The first processing unit includes a plurality of subprocessing units and buffers, and the second processing unit also includes a plurality of subprocessing units and buffers. The second processing unit includes a storage. The monitor includes a first monitor that monitors, for each of the buffers included in the first processing unit, an amount of the data stored in the corresponding buffer and a second monitor that monitors a total amount of the data stored in the buffers included in the second processing unit and the data stored in the storage.

A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

A device is disclosed that includes multiple channels and multiple processing nodes. Each processing node includes input/output (I/O) ports coupled to the channels and channel control modules coupled to the I/O ports. Each processing node is configured to select, by the channel control module in a first operation, a first I/O port of the I/O ports; communicate a first message, via the first I/O port, to a first processing node over a first channel or a second processing node over a second channel orthogonal to the first channel in a logic representation; select, by the channel control module in a second operation, a second I/O port of the I/O ports; and communicate a second message, via the second I/O port, to a third processing node over a third channel extending in a diagonal direction and non-orthogonal to the first and second channels in the logic representation.

A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

A chiplet system and a positioning method thereof are provided. The positioning method of the chiplet system includes the following steps. Two end chiplets and a plurality of middle chiplets are classified. A quantity calculation packet is transmitted and accumulated from each of the end chiplets towards another end to analyze a quantity of middle chiplets. A serial number comparison packet is transmitted and accumulated from each of the middle chiplets connected to one of the end chiplets towards another end to set a starting point. An identify number setting packet is transmitted and accumulated from the middle chiplet set as the starting point towards another end to set a positioning number of each of the middle chiplets.

An apparatus stores connection information indicating connection relationship among topological structures in a network, in which first-type topological structures are coupled to second-type topological structures. The apparatus stores first transfer-patterns each indicating a combination of input and output ports for performing all-to-all communication without path conflict in each of the first-type topological structures, and second transfer-patterns each indicating a combination of input and output ports for performing all-to-all communication without path conflict in each of the second-type topological structures. The apparatus identifies paths from transmission sources to transmission destinations for a combination of the first and second transfer-patterns, and determines, based on the identified paths, a transfer-pattern with which to perform all-to-all communication without path conflict from the transmission sources to the transmission destinations, and determines output ports in each of the first- and second-type topological structures, corresponding to the identified paths.