Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

A processor in a network has a plurality of processing units arranged on a chip. An on-chip interconnect enables data to be exchanged between the processing units. A plurality of external interfaces are configured to communicate data off chip in the form of packets, each packet having a destination address identifying a destination of the packet. The external interfaces are connected to respective additional connected processors. A routing bus routes packets between the processing units and the external interfaces. A routing register defines a routing domain for the processor, the routing domain comprising one or more of the additional processor, and at least a subset of further additional processors of the network, wherein the additional processors of the subset are directly or indirectly connected to the processor. The routing domain can be modified by changing the contents of the routing register as a sliding window domain.

A data processing system comprising a plurality of processing units. Each processing unit comprises a set of plural functional units and an internal communications network that routes communications between the functional units in a particular sequence order of the functional units. Each processing unit is connected to at least one other processing unit via a communications bridge that has at least two connections, a first connection that routes communications between a first pair of network nodes of the pair of processing units, and a separate, second connection that routes communications between a second, different pair of network nodes of the pair of processing units. Each connected pair of network nodes comprises network nodes having different positions in the internal communications network sequence order of the network nodes and/or network nodes associated with functional units of different types.

A plurality of processing elements (PEs) include memory local to at least one of the processing elements in a data packet-switched network interconnecting the processing elements and the memory to enable any of the PEs to access the memory. The network consists of nodes arranged linearly or in a grid to connect the PEs and their local memories to a common controller. The processor performs memory accesses on data stored in the memory in response to control signals sent by the controller to the memory. The local memories share the same memory map or space. The packet-switched network supports multiple concurrent transfers between PEs and memory. Memory accesses include block and/or broadcast read and write operations, in which data can be replicated within the nodes and, according to the operation, written into the shared memory or into the local PE memory.

In one aspect of the teachings herein, a Services Capability Layer, SCL, within a Machine-to-Machine, M2M, network generates unique identifiers, for use in identifying individual application instances within the M2M domain. According to such operation, an SCL receives or otherwise obtains an application identifier for an application instance registering at the SCL, and generates a globally unique identifier for the application instance using the application identifier or an alias corresponding to it. As an example, the SCL appends to the application identifier or alias its own identifier, which is unique to that SCL, along with a random value. The resultant identifier is guaranteed to be unique for the individual application instance and the SCL uses the resultant identifier for identifying the application instance to other entities within the M2M domain.

This invention discloses a novel paradigm, method and apparatus for Matrix Computing which include a novel machine architecture with an embedded storage space for holding matrices and arrays for computing which can be accessed by its columns or by its rows or both concurrently. A large capacity multi length instruction set with instructions and methods to load, store and compute with these matrices and arrays are also disclosed; a method and apparatus to secure, share, lock and unlock this embedded space for matrices under the control of an Operating System or a Virtual Machine Monitor by a plurality of threads and processes are also disclosed. A novel method and apparatus to handle immediate operands used by Immediate Instructions are also disclosed. The structure of the instructions with some key fields and a method for determining instruction length easily are also disclosed.

A network overlay system can include a data transport module having a network interface and a translation module configured to generate offload processing addresses for the network packet data; a system bus; at least one host processor connected to the system bus; and at least one offload processor module coupled to the system bus and configured to receive network packet data associated. Offload processor modules include processing circuits associated with at least one of the offload processing addresses that are configured to encapsulate the network packet data for transport on a logical network or decapsulate the network packet data received from the logical network. The offload processing circuits encapsulate or decapsulate network packet data independent of any host processor.

Embodiments herein describe a computing system which is reconfigurable into different server configurations that have different numbers of sockets. For example, the computing system may include two server nodes which can be configured into either two independent servers (i.e., two 2S servers) or a single server (i.e., one 4S server). In one embodiment, the computing system includes a midplane which is connected to processor buses on the server nodes. When configured as a single server, the midplane connects the processor bus (or buses) on one of the server nodes to the processor bus or buses on the other server node. In this manner, the processors in the two server nodes can be interconnected to function as a single server. In contrast, the connections between the server nodes in the midplane are disabled when the server nodes operate as two independent servers.

Systems and methods involve receiving requests to execute different processing tasks in a data processing system including first and second manycore processor units each having a processing unit and a programmable logic component, causing the tasks to be performed in different instances on the first processing unit and the first programmable logic component of the first manycore processor unit and on the second processing unit and the second programmable logic component of the second manycore processor unit including, in a particular instance, causing a particular task to be performed locally on the first programmable logic component based at least on a mapping consideration, and in another instance, partially reconfiguring the second programmable logic component to perform another task responsive to determining that the second programmable logic component is not already configured to perform the task.

In embodiments of the present disclosure, there is provided a solution for establishing a socket connection in a user space. After receiving a request for establishing a socket connection from a first application, the monitor sends the connection request to a second application, wherein the first application and the second application run on the same computing device. Then, the monitor coordinates establishing, in user space of the operating system, a peer-to-peer socket connection between the first application and the second application. By establishing a socket connection in the user space of the operating system, embodiments of the present disclosure can achieve a user space socket connection between different applications within a single computing device, thereby improving the performance of the operating system. In addition, embodiments of the present disclosure use the monitor (or controller) to coordinate inter-application connection establishment and resource allocation, thereby ensuring security of the operating system.