An infrastructure for a platform immersive experience is described. An example of an apparatus includes a microcontroller to receive control parameters for platform lighting options for a computing system and information regarding current system conditions for the computing system, and generate control instructions for a lighting pattern for a set of lights based at least in part on the control parameters and the information regarding current system conditions; and host control circuitry to receive the control instructions for the lighting pattern from the microcontroller, and provide control signals to control the set of lights.

A retimer device is presented with a retimer with an array of connectors on a surface of the device that are configured to form a ball grid array to electrically connect the chip package to a circuit board. At least a portion of the connectors in the array are arranged on the surface in a hexagonal pattern. The connectors are assigned to the plurality of high speed connectors to arrange each high speed differential pair in the plurality of high speed differential pairs substantially orthogonally with respect to one or more other differential pairs in the plurality of high speed differential pairs.

Embodiments are disclosed for a standardized car interface for cockpit controllers in vehicles. In one example, a system for coupling a vehicle cable for communication with components of an infotainment system, comprises: a housing, a domain controller, and a first connector interface including all connections for the domain controller. In the event that a first domain controller is exchanged for a second domain controller, a collection of user preferences may be transferred between the first domain controller to the second domain controller.

A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

A method includes reading first and second timer count values from a timer. The first timer count value is associated with a first time point, and the second timer count value is associated with a second time point. Also, the method includes calculating a difference between the first and the second timer count values, and determining whether the difference is within a range. The range is based on a desired executing frequency to perform a computing task, a variation of the desired executing frequency, and a timer frequency. Further, based on the difference not being within the range, the method includes setting an error flag value to be true and incrementing an error count value.

A system to support data gathering for a machine learning (ML) operation comprises a memory unit configured to maintain data for the ML operation in a plurality of memory blocks each accessible via a memory address. The system further comprises an inference engine comprising a plurality of processing tiles each comprising one or more of an on-chip memory (OCM) configured to load and maintain data for local access by components in the processing tile. The system also comprises a core configured to program components of the processing tiles of the inference engine according to an instruction set architecture (ISA) and a data streaming engine configured to stream data between the memory unit and the OCMs of the processing tiles of the inference engine wherein data streaming engine is configured to perform a data gathering operation via a single data gathering instruction of the ISA at the same time.

Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.

A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.

The reliability of a data communication link may be analyzed and otherwise maintained by collecting a two-dimensional array representing a functional data eye, and using a convolutional neural network to determine a score of the functional data eye. The determined score may be compared with a threshold, and an action may be initiated based on the result of the comparison.

Disclosed herein is a multiprocessor system for facilitating real-time multitasking processing. The multiprocessor system may include a task scheduler and a plurality of processors. Further, the task scheduler may be configured for receiving an event associated with the multiprocessor system, evaluating a plurality of task priorities associated with a plurality of tasks based on the event, determining a plurality of new task priorities for the plurality of tasks and assigning the plurality of tasks to a plurality of lists based on the determining. Further, the plurality of processors may be communicatively coupled with the task scheduler. Further, the plurality of processors serves the plurality of lists. Further, a processor of the plurality of processors may be configured for processing the plurality of tasks assigned to a list of the plurality of lists based on the plurality of new task priorities.