A neural network accelerator is provided, including: a preprocessing module (301), configured to perform first forward winograd transform on a target matrix corresponding to an input feature map, to obtain a transformed target matrix, where the preprocessing module (301) is further configured to perform second forward winograd transform on a convolution kernel, to obtain a transformed convolution kernel; a matrix operation module (302), configured to perform a matrix multiplication operation on a first matrix and a second matrix, to obtain a multiplication result, where the first matrix is constructed based on the transformed target matrix, and the second matrix is constructed based on the transformed convolution kernel; and a vector operation module (303), configured to perform inverse winograd transform on the multiplication result, to obtain an output feature map.

Technologies for providing deduplication of data in an edge network includes a compute device having circuitry to obtain a request to write a data set. The circuitry is also to apply, to the data set, an approximation function to produce an approximated data set. Additionally, the circuitry is to determine whether the approximated data set is already present in a shared memory and write, to a translation table and in response to a determination that the approximated data set is already present in the shared memory, an association between a local memory address and a location, in the shared memory, where the approximated data set is already present. Additionally, the circuitry is to increase a reference count associated with the location in the shared memory.

Technologies for providing deduplication of data in an edge network includes a compute device having circuitry to obtain a request to write a data set. The circuitry is also to apply, to the data set, an approximation function to produce an approximated data set. Additionally, the circuitry is to determine whether the approximated data set is already present in a shared memory and write, to a translation table and in response to a determination that the approximated data set is already present in the shared memory, an association between a local memory address and a location, in the shared memory, where the approximated data set is already present. Additionally, the circuitry is to increase a reference count associated with the location in the shared memory.

A method for operating on a target function to provide computer code instructions configured to implement automatic adjoint differentiation of the target function. The method comprises: determining, based on the target function, a linearized computational map (100), LCM, of the target function wherein each node of the LCM (100) comprises an elementary operation; for each node of the LCM (100) forming computer code instructions configured to: (i) compute intermediate data associated with a forward function of an automatic adjoint differentiation algorithm; and, (ii) increment, according to the automatic adjoint differentiation algorithm, adjoint variables of the preceding connected nodes of the each node in dependence on intermediate data; wherein forming computer code instructions for both step (i) and step (ii) for each node is performed prior to performing said steps for a subsequent node of the LCM (100).

A method for operating on a target function to provide computer code instructions configured to implement automatic adjoint differentiation of the target function. The method comprises: determining, based on the target function, a linearized computational map (100), LCM, of the target function wherein each node of the LCM (100) comprises an elementary operation; for each node of the LCM (100) forming computer code instructions configured to: (i) compute intermediate data associated with a forward function of an automatic adjoint differentiation algorithm; and, (ii) increment, according to the automatic adjoint differentiation algorithm, adjoint variables of the preceding connected nodes of the each node in dependence on intermediate data; wherein forming computer code instructions for both step (i) and step (ii) for each node is performed prior to performing said steps for a subsequent node of the LCM (100).

A spurious outlier detection-system is provided. The system includes a memory having computer-readable instructions stored therein and a processor configured to execute the computer-readable instructions to receive time-series data from one or more sensors and/or applications, process the time-series data to detect one or more change points based on a pre-defined cost function. The processor is configured to identify data chunks between the change points using pre-determined window sizes and to estimate smooth reconstructed values (SRVs) for each of the change point data chunks between two consecutive change points to identify one or more global outliers from the SRVs. The processor is configured to determine distribution of the global outliers using kernel density for each change point data chunk and identify one or more true outliers from the distribution of the global outliers based upon a skewness of the distribution.

An execution unit comprising a processing pipeline configured to perform calculations to evaluate a plurality of mathematical functions. The processing pipeline comprises a plurality of stages through which each calculation for evaluating a mathematical function progresses to an end result. Each of a plurality of processing circuits in the pipeline is configured to perform an operation on input values during at least one stage of the plurality of stages. The plurality of processing circuits include multiplier circuits. A first multiplier circuit and a second multiplier circuit are configured to operate in parallel, such that at the same stage in the processing pipeline, the first multiplier circuit and the second multiplier circuit perform their processing. A third multiplier circuit is arranged in series with the first multiplier circuit and the second multiplier circuit and processes outputs from the first multiplier circuit and the second multiplier circuit.

Methods of designing a polynucleotide sequence for expressing a polypeptide-of-interest in a cell are provided. Also provided are artificial transcript sequences generated according to the present teachings. Further provided are methods of estimating the adaptiveness of a transcript sequence encoding a polypeptide-of-interest to a gene expression machinery in a cell.

Methods of designing a polynucleotide sequence for expressing a polypeptide-of-interest in a cell are provided. Also provided are artificial transcript sequences generated according to the present teachings. Further provided are methods of estimating the adaptiveness of a transcript sequence encoding a polypeptide-of-interest to a gene expression machinery in a cell.

A method for differentiator-based compression of digital data includes (a) multiplying a tap-weight vector by an original data vector to generate a predicted signal, the original data vector comprising N sequential samples of an original signal, N being an integer greater than or equal to one, (b) using a subtraction module, subtracting the predicted signal from a sample of the original signal to obtain an error signal, (c) using a quantization module, quantizing the error signal to obtain a quantized error signal, and (d) updating the tap-weight vector according to changing statistical properties of the original signal.