A calculation processor for determining a digital output value from a digital input value based on an exponent value a, the processor comprising a first calculation block, a second calculation block and a final calculation block. The first calculation block initializes an intermediate value and an error value depending on a position of a Most Significant Bit of a significant part of the input value. The second calculation block is configured to perform repeatedly, until an exit criterion is fulfilled, the incrementation of a counter value, the determination of a power error value based on the error value and, if the power error value is larger than or equal to an error threshold, adjustment of the intermediate value y by multiplying the intermediate value with an adaptation value and setting the error value to the power error value divided by the base value. If the power error value is smaller than the error threshold, the error value is set to the power error value. The final calculation block is configured to set the output value to the intermediate value.

A process for computing the optimal solution to the quadratic assignment problem (QAP) defined on lattices includes storing facility data as facilities in a facility grid with facility tiles. Location data are stored as locations in a location grid with location tiles. Each facility tile is associated with a location tile and each facility in each facility tile is associated with a location in an associated location tile. A flow function is identified as distances between the plurality of facilities in the facility grid, and a distance function is identified as distances between the plurality of locations in the location grid. An association function relating the facilities to the locations is identified such that a solution with a low-cost function depending on the flow function and the distance function is found.

A calculation processor for determining a digital output value (OUT) from a digital input value (IN) based on an exponent value a, the processor comprising a first calculation block (CB1), a second calculation block (CB2) and a final calculation block (CBF). The first calculation block (CB1) initializes an intermediate value and an error value depending on a position of a Most Significant Bit of a significant part of the input value. The second calculation block is configured to perform repeatedly, until an exit criterion is fulfilled, the incrementation of a counter value, the determination of a power error value based on the error value and, if the power error value is larger than or equal to an error threshold, adjustment of the intermediate value y by multiplying the intermediate value with an adaptation value and setting the error value to the power error value divided by the base value. If the power error value is smaller than the error threshold, the error value is set to the power error value. The final calculation block is configured to set the output value to the intermediate value.

A method of measuring a movement, the method comprising the steps of: acquiring and digitizing both a first measurement voltage across the terminals of a first secondary winding and also a second measurement voltage across the terminals of a second secondary winding of an inductive movement sensor; multiplying the first measurement voltage by itself in order to obtain a first component of a crossed vector, multiplying the second measurement voltage by itself in order to obtain a second component of the crossed vector, and multiplying together the first measurement voltage and the second measurement voltage in order to obtain a third component of the crossed vector; applying the crossed vector as input to a lowpass filter in order to obtain a filtered vector, and estimating the movement from the components of the filtered vector.

A method of measuring a movement, the method comprising the steps of: acquiring and digitizing both a first measurement voltage across the terminals of a first secondary winding and also a second measurement voltage across the terminals of a second secondary winding of an inductive movement sensor; multiplying the first measurement voltage by itself in order to obtain a first component of a crossed vector, multiplying the second measurement voltage by itself in order to obtain a second component of the crossed vector, and multiplying together the first measurement voltage and the second measurement voltage in order to obtain a third component of the crossed vector; applying the crossed vector as input to a lowpass filter in order to obtain a filtered vector; and estimating the movement from the components of the filtered vector.

Control circuitry coupled to a multiply unit which includes a plurality of stage, each of which may be configured to perform a corresponding arithmetic function, may be configured to retrieve a given entry from a lookup table dependent upon a first portion of a binary representation of an input operand. An error value of an error function evaluated dependent upon a lookup value in a given entry of the plurality of entries is included in a predetermined error range. The control circuitry may be further configured to determine an initial approximation of a result of an iterative arithmetic operation using the first entry and initiate the iterative arithmetic operation using the initial approximation and the input operand.

Control circuitry coupled to a multiply unit which includes a plurality of stage, each of which may be configured to perform a corresponding arithmetic function, may be configured to retrieve a given entry from a lookup table dependent upon a first portion of a binary representation of an input operand. An error value of an error function evaluated dependent upon a lookup value in a given entry of the plurality of entries is included in a predetermined error range. The control circuitry may be further configured to determine an initial approximation of a result of an iterative arithmetic operation using the first entry and initiate the iterative arithmetic operation using the initial approximation and the input operand.

A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital hardware calculator for parallel computation. The digital hardware calculator and the MAC may be coupled to an input memory element for receipt of input operands. The MAC may include a digital multiplier structure with partial product generators coupled to an adder to multiply a first and second input operands and generate a multiplication result. The digital hardware calculator may include a first look-up table coupled between a calculator input and a calculator output register. The first look-up table may include table entry values mapped to corresponding math function results in accordance with a first predetermined mathematical function. The digital hardware calculator may be configured to calculate, based on the first look-up table, a computationally hard mathematical function such as a logarithm function, an exponential function, a division function and a square root function.

Mathematical functions are computed in a single pipeline performing a polynomial approximation (e.g. a quadratic approximation, or the like) using data tables for RCP, SQRT, EXP or LOG using a single pipeline according and opcodes. SIN and COS are also computed using the pipeline according to the approximation ((1)^IntX)*Sin(*Min(FracX, 1.0FracX)/Min(FracX, 1.0FracX). A pipeline portion approximates Sin(*FracX) using tables and interpolation and a subsequent stage multiplies this approximation by FracX. For input arguments of x close 1.0. LOG 2(x1)/(x1) is computed using a first pipeline portion using tables and interpolation and subsequently multiplied by (x1). A DIV operation may also be performed with input arguments scaled up to avoid underflow as needed. Inverse trigonometric functions may be calculated using a pre-processing stage and post processing stage in order to obtain multiple inverse trigonometric functions from a single pipeline.

A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C0+C1X2+C2X2.sup.2. The functional unit has a multiplier circuit. The multiplier circuit has: i) a first input to receive bits of a first operand of the first instruction and receive bits of a C1 term of the second instruction; ii) a second input to receive bits of a second operand of the first instruction and receive bits of a X2 term of the second instruction.